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    Flexible structures for interconnect reliability test
    3.
    发明授权
    Flexible structures for interconnect reliability test 有权
    用于互连可靠性测试的柔性结构

    公开(公告)号：US07776627B2

    公开(公告)日：2010-08-17

    申请号：US11971072

    申请日：2008-01-08

    申请人： Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu

    发明人： Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu

    IPC分类号： H01L21/66

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.

    摘要翻译： 一种用于形成集成电路结构的方法包括形成测试晶片。 形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。 第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。 每个连接块单元包括两个连接块和连接两个连接块的金属线。 该方法还包括形成将第一多个单元块彼此分离的多个单元块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。

    Protective seal ring for preventing die-saw induced stress
    4.
    发明授权
    Protective seal ring for preventing die-saw induced stress 有权
    用于防止模锯引起的应力的保护密封环

    公开(公告)号：US08334582B2

    公开(公告)日：2012-12-18

    申请号：US12347026

    申请日：2008-12-31

    申请人： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu ,  Yu-Wen Liu

    发明人： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu ,  Yu-Wen Liu

    IPC分类号： H01L23/544

    CPC分类号： H01L21/78 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.

    摘要翻译： 半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。 第一密封环邻近半导体芯片的边缘，其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。 第二密封环与第一密封环相邻，并且在半导体芯片的内侧与第一密封环相邻。 第二密封环包括在第一钝化层和第二钝化层中的焊盘环。 沟槽环包括直接在第一密封环上的至少一部分。 沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。