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公开(公告)号:US08334582B2
公开(公告)日:2012-12-18
申请号:US12347026
申请日:2008-12-31
申请人: Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu , Yu-Wen Liu
发明人: Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu , Yu-Wen Liu
IPC分类号: H01L23/544
CPC分类号: H01L21/78 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.
摘要翻译: 半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。 第一密封环邻近半导体芯片的边缘,其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。 第二密封环与第一密封环相邻,并且在半导体芯片的内侧与第一密封环相邻。 第二密封环包括在第一钝化层和第二钝化层中的焊盘环。 沟槽环包括直接在第一密封环上的至少一部分。 沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。
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公开(公告)号:US08227917B2
公开(公告)日:2012-07-24
申请号:US11868850
申请日:2007-10-08
申请人: Shih-Hsun Hsu , Hao-Yi Tsai , Benson Liu , Chia-Lun Tsai , Hsien-Wei Chen , Anbiarshy N. F. Wu , Shang-Yun Hou , Shin-Puu Jeng
发明人: Shih-Hsun Hsu , Hao-Yi Tsai , Benson Liu , Chia-Lun Tsai , Hsien-Wei Chen , Anbiarshy N. F. Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号: H01L23/48
CPC分类号: H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/05552 , H01L2224/05599 , H01L2224/0603 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082
摘要: A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad.
摘要翻译: 公开了一种焊盘设计,其包括半导体器件上的一个或多个焊盘组。 每个焊盘组由具有交替取向的两个或更多个焊盘组成,使得相邻的焊盘相对于相邻的焊盘在相对的两侧具有焊接球。
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公开(公告)号:US09859235B2
公开(公告)日:2018-01-02
申请号:US12619503
申请日:2009-11-16
申请人: Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
发明人: Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
IPC分类号: H01L23/488 , H01L23/00 , H01L23/31
CPC分类号: H01L24/05 , H01L23/3157 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0215 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05027 , H01L2224/0508 , H01L2224/05096 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05541 , H01L2224/05552 , H01L2224/05553 , H01L2224/05557 , H01L2224/05558 , H01L2224/05566 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13005 , H01L2224/13007 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/05442 , H01L2924/00014 , H01L2924/2064 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要: A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.
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公开(公告)号:US20100123219A1
公开(公告)日:2010-05-20
申请号:US12347184
申请日:2008-12-31
申请人: Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
发明人: Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
IPC分类号: H01L23/544
CPC分类号: H01L23/3677 , B23K26/364 , B23K26/40 , B23K2103/172 , H01L21/78 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要: An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.
摘要翻译: 集成电路结构包括:第一芯片,包括第一边缘; 以及具有面向第一边缘的第二边缘的第二芯片。 划线在第一边缘和第二边缘之间并相邻。 散热器包括划线中的一部分,其中散热器包括多个通孔和多个金属线。 散热器在划线中的部分具有至少接近或大于第一边缘的第一长度的第二长度。
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公开(公告)号:US20110127648A1
公开(公告)日:2011-06-02
申请号:US13023151
申请日:2011-02-08
申请人: Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
发明人: Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
IPC分类号: H01L23/544 , H01L23/34
CPC分类号: H01L23/3677 , B23K26/364 , B23K26/40 , B23K2103/172 , H01L21/78 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要: An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.
摘要翻译: 集成电路结构包括:第一芯片,包括第一边缘; 以及具有面向第一边缘的第二边缘的第二芯片。 划线在第一边缘和第二边缘之间并相邻。 散热器包括划线中的一部分,其中散热器包括多个通孔和多个金属线。 散热器在划线中的部分具有至少接近或大于第一边缘的第一长度的第二长度。
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公开(公告)号:US07906836B2
公开(公告)日:2011-03-15
申请号:US12347184
申请日:2008-12-31
申请人: Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
发明人: Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
IPC分类号: H01L23/34
CPC分类号: H01L23/3677 , B23K26/364 , B23K26/40 , B23K2103/172 , H01L21/78 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要: An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.
摘要翻译: 集成电路结构包括:第一芯片,包括第一边缘; 以及具有面向第一边缘的第二边缘的第二芯片。 划线在第一边缘和第二边缘之间并相邻。 散热器包括划线中的一部分,其中散热器包括多个通孔和多个金属线。 散热器在划线中的部分具有至少接近或大于第一边缘的第一长度的第二长度。
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公开(公告)号:US20100187687A1
公开(公告)日:2010-07-29
申请号:US12619503
申请日:2009-11-16
申请人: Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
发明人: Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
IPC分类号: H01L23/488 , H01L21/60
CPC分类号: H01L24/05 , H01L23/3157 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0215 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05027 , H01L2224/0508 , H01L2224/05096 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05541 , H01L2224/05552 , H01L2224/05553 , H01L2224/05557 , H01L2224/05558 , H01L2224/05566 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13005 , H01L2224/13007 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/05442 , H01L2924/00014 , H01L2924/2064 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要: A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.
摘要翻译: 提出了一种用于形成底部金属化(UBM)的系统和方法。 优选实施例包括凸起的UBM,其延伸穿过钝化层以便与接触焊盘接触,同时在接触焊盘和UBM之间保留足够的钝化层以充分地处理由CTE失配引起的剥离和剪切应力, 后续热处理。 UBM触点优选地形成为八边形环形或触点阵列。
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公开(公告)号:US08860208B2
公开(公告)日:2014-10-14
申请号:US13023151
申请日:2011-02-08
申请人: Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
发明人: Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
CPC分类号: H01L23/3677 , B23K26/364 , B23K26/40 , B23K2103/172 , H01L21/78 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要: An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.
摘要翻译: 集成电路结构包括:第一芯片,包括第一边缘; 以及具有面向第一边缘的第二边缘的第二芯片。 划线在第一边缘和第二边缘之间并相邻。 散热器包括划线中的一部分,其中散热器包括多个通孔和多个金属线。 散热器在划线中的部分具有至少接近或大于第一边缘的第一长度的第二长度。
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公开(公告)号:US20090321890A1
公开(公告)日:2009-12-31
申请号:US12347026
申请日:2008-12-31
申请人: Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N.F. Wu , Yu-Wen Liu
发明人: Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N.F. Wu , Yu-Wen Liu
IPC分类号: H01L23/10
CPC分类号: H01L21/78 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.
摘要翻译: 半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。 第一密封环邻近半导体芯片的边缘,其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。 第二密封环与第一密封环相邻,并且在半导体芯片的内侧与第一密封环相邻。 第二密封环包括在第一钝化层和第二钝化层中的焊盘环。 沟槽环包括直接在第一密封环上的至少一部分。 沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。
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公开(公告)号:US07776627B2
公开(公告)日:2010-08-17
申请号:US11971072
申请日:2008-01-08
申请人: Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu
发明人: Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu
IPC分类号: H01L21/66
CPC分类号: H01L22/34 , H01L2924/0002 , H01L2924/00
摘要: A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.
摘要翻译: 一种用于形成集成电路结构的方法包括形成测试晶片。 形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。 第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。 每个连接块单元包括两个连接块和连接两个连接块的金属线。 该方法还包括形成将第一多个单元块彼此分离的多个单元块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。
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