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    Deferred queuing in a buffered switch
    3.
    发明授权
    Deferred queuing in a buffered switch 有权
    在缓冲交换机中延迟排队

    公开(公告)号：US07773622B2

    公开(公告)日：2010-08-10

    申请号：US10873430

    申请日：2004-06-21

    申请人： Steven G. Schmidt ,  Anthony G. Tornetta ,  Harry V. Paul ,  Henry J. Gonzalez

    发明人： Steven G. Schmidt ,  Anthony G. Tornetta ,  Harry V. Paul ,  Henry J. Gonzalez

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  H04L49/30 ,  H04L2012/5683

    摘要： A method and apparatus is disclosed for temporarily deferring transmission of frames to a destination in a data switch. When a request for transmission of a frame to the destination port is received, the congestion status of that destination is determined. If the destination is congested, the frame is stored in a deferred queue. When the status of a destination changes from congested to non-congested, the deferred queue is examined to see if any deferred frames can now be forwarded to their destination. While examining the deferred queue, incoming frames are placed on a backup queue. When the deferred queue is fully analyzed, the backup queue is emptied by either sending those frames to their destination or storing the frames in the deferred queue. While examining the deferred queue, the congested states of the destinations are not allowed to change from congested to non-congested.

    摘要翻译： 公开了一种用于在数据交换机中暂时推迟到目的地传送帧的方法和装置。 当接收到向目的地端口发送帧的请求时，确定该目的地的拥塞状态。 如果目的地拥塞，则将帧存储在延迟队列中。 当目的地状态从拥塞状态改变为非拥塞状态时，会检查延迟队列，以查看是否有任何延迟帧现在可以转发到其目的地。 在检查延迟队列时，传入帧将放置在备份队列中。 当延迟队列被完全分析时，通过将这些帧发送到其目的地或将帧存储在延迟队列中，备份队列将被清空。 在检查延期队列时，目的地的拥塞状态不允许从拥塞状态改为非拥塞状态。

    Deferred queuing in a buffered switch
    5.
    发明授权
    Deferred queuing in a buffered switch 有权
    在缓冲交换机中延迟排队

    公开(公告)号：US08379658B2

    公开(公告)日：2013-02-19

    申请号：US12826959

    申请日：2010-06-30

    申请人： Steven G. Schmidt ,  Anthony G. Tornetta ,  Harry V. Paul ,  Henry J. Gonzalez

    发明人： Steven G. Schmidt ,  Anthony G. Tornetta ,  Harry V. Paul ,  Henry J. Gonzalez

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  H04L49/30 ,  H04L2012/5683

    摘要： A method and apparatus is disclosed for temporarily deferring transmission of frames to a destination in a data switch. When a request for transmission of a frame to the destination port is received, the congestion status of that destination is determined. If the destination is congested, the frame is stored in a deferred queue. When the status of a destination changes from congested to non-congested, the deferred queue is examined to see if any deferred frames can now be forwarded to their destination. While examining the deferred queue, incoming frames are placed on a backup queue. When the deferred queue is fully analyzed, the backup queue is emptied by either sending those frames to their destination or storing the frames in the deferred queue. While examining the deferred queue, the congested states of the destinations are not allowed to change from congested to non-congested.

    摘要翻译： 公开了一种用于在数据交换机中暂时推迟到目的地传送帧的方法和装置。 当接收到向目的地端口发送帧的请求时，确定该目的地的拥塞状态。 如果目的地拥塞，则将帧存储在延迟队列中。 当目的地状态从拥塞状态改变为非拥塞状态时，会检查延迟队列，以查看是否有任何延迟帧现在可以转发到其目的地。 在检查延迟队列时，传入帧将放置在备份队列中。 当延迟队列被完全分析时，通过将这些帧发送到其目的地或将帧存储在延迟队列中，备份队列将被清空。 在检查延期队列时，目的地的拥塞状态不允许从拥塞状态改为非拥塞状态。

    Deferred Queuing in a Buffered Switch
    6.
    发明申请
    Deferred Queuing in a Buffered Switch 有权
    缓冲交换机中的延迟队列

    公开(公告)号：US20100265821A1

    公开(公告)日：2010-10-21

    申请号：US12826959

    申请日：2010-06-30

    申请人： Steven G. Schmidt ,  Anthony G. Tornetta ,  Harry V. Paul ,  Henry J. Gonzalez

    发明人： Steven G. Schmidt ,  Anthony G. Tornetta ,  Harry V. Paul ,  Henry J. Gonzalez

    IPC分类号： H04L12/24

    CPC分类号： H04L49/3009 ,  H04L49/30 ,  H04L2012/5683

    摘要： A method and apparatus is disclosed for temporarily deferring transmission of frames to a destination in a data switch. When a request for transmission of a frame to the destination port is received, the congestion status of that destination is determined. If the destination is congested, the frame is stored in a deferred queue. When the status of a destination changes from congested to non-congested, the deferred queue is examined to see if any deferred frames can now be forwarded to their destination. While examining the deferred queue, incoming frames are placed on a backup queue. When the deferred queue is fully analyzed, the backup queue is emptied by either sending those frames to their destination or storing the frames in the deferred queue. While examining the deferred queue, the congested states of the destinations are not allowed to change from congested to non-congested.

    摘要翻译： 公开了一种用于在数据交换机中暂时推迟到目的地传送帧的方法和装置。 当接收到向目的地端口发送帧的请求时，确定该目的地的拥塞状态。 如果目的地拥塞，则将帧存储在延迟队列中。 当目的地状态从拥塞状态改变为非拥塞状态时，会检查延迟队列，以查看是否有任何延迟帧现在可以转发到其目的地。 在检查延迟队列时，传入帧将放置在备份队列中。 当延迟队列被完全分析时，通过将这些帧发送到其目的地或将帧存储在延迟队列中，备份队列将被清空。 在检查延期队列时，目的地的拥塞状态不允许从拥塞状态改为非拥塞状态。

    Clock compensation circuit
    7.
    发明授权
    Clock compensation circuit 失效
    时钟补偿电路

    公开(公告)号：US6023180A

    公开(公告)日：2000-02-08

    申请号：US195419

    申请日：1998-11-17

    申请人： Steven G. Schmidt

    发明人： Steven G. Schmidt

    IPC分类号： G06F1/10 ,  H03K5/13

    CPC分类号： G06F1/10 ,  H03K5/133

    摘要： A clock compensation circuit includes a clock tree; a reference clock; a phase detector for detecting relative phase information of the tree clock and the reference clock; a controller, coupled to said phase detector, for determining and controlling the amount of delay necessary to shift the output of the clock tree in phase with the reference clock; and a programmable delay logic coupled to said controller. The programmable delay logic comprises a string of delay elements that selectively participate in a delay string for shifting the tree clock in phase with the reference clock.

    摘要翻译： 时钟补偿电路包括时钟树; 参考时钟 相位检测器，用于检测树时钟和参考时钟的相对相位信息; 耦合到所述相位检测器的控制器，用于确定和控制与参考时钟同相移位时钟树的输出所需的延迟量; 以及耦合到所述控制器的可编程延迟逻辑。 可编程延迟逻辑包括一组延迟元件，其选择性地参与用于与参考时钟同相移位树状时钟的延迟串。

    Deferred queuing in a buffered switch
    8.
    发明授权
    Deferred queuing in a buffered switch 有权
    在缓冲交换机中延迟排队

    公开(公告)号：US07260104B2

    公开(公告)日：2007-08-21

    申请号：US10020968

    申请日：2001-12-19

    申请人： Steven G. Schmidt

    发明人： Steven G. Schmidt

    IPC分类号： H04L12/56

    CPC分类号： H04L49/3009 ,  H04L49/30 ,  H04L2012/5683

    摘要： A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.

    摘要翻译： 公开了一种用于暂时将缓存的交换机中的分组/帧传输到目的地端口的方法和装置。 当接收到至少一个分组/帧到目的地端口的传输请求时，确定目的端口是否可用于接收至少一个分组/帧。 当目的地端口不可用于接收至少一个分组/帧时，延迟至少一个分组/帧的传输。 每个延迟分组/帧的分组/帧标识符和存储器位置被存储在延迟队列中，然后该过程重复下一个分组/帧。 周期性地，设备尝试将延迟队列中的分组/帧传送到它们各自的目的端口。

    Fault tolerant switch fabric with control and data correction by hamming codes and error inducing check register
    9.
    发明授权
    Fault tolerant switch fabric with control and data correction by hamming codes and error inducing check register 失效
    容错开关结构，通过汉明码和错误引导检查寄存器进行控制和数据校正

    公开(公告)号：US5812556A

    公开(公告)日：1998-09-22

    申请号：US675491

    申请日：1996-07-03

    申请人： Steven G. Schmidt

    发明人： Steven G. Schmidt

    IPC分类号： H04L1/00 ,  H04L1/24 ,  H04Q3/545 ,  H04Q11/04 ,  H04J3/14

    CPC分类号： H04L1/0057 ,  H04L1/24 ,  H04Q11/04 ,  H04Q3/54591 ,  H04Q2213/13003 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13166 ,  H04Q2213/13167 ,  H04Q2213/13168 ,  H04Q2213/13174 ,  H04Q2213/13213 ,  H04Q2213/13215 ,  H04Q2213/13292 ,  H04Q2213/13299

    摘要： There is provided a dynamic switch organization for error correction of a data path. The dynamic switch organization includes a data path for transmitting data information and control information and a crosspoint switch fabric having a plurality of inputs and a plurality of outputs along the data path. The crosspoint switch fabric has an arbitration bus and crosspoint switch boards coupled to the arbitration bus such that the boards are synchronized to process data in parallel. The crosspoint switch fabric also includes a control entity for directing data from one of the inputs to a particular one of the outputs, and the data includes data bits and check bits. The control entity is distributed among the crosspoint switch boards such that each board includes a portion of the control entity. In addition, the crosspoint switch fabric includes error correction mechanism for applying an error correction scheme, namely a Hamming error correction scheme, to the data and check bits so that the error correction mechanism identifies an erroneous bit and inverts the erroneous bit in order to form corrected data. An improvement is provided to the error correction scheme by adding a feature which allows for checking whether the scheme is operating properly; to enable, checking by means of diagnostic software, an error is deliberately introduced on a particular data bit.

    摘要翻译： 提供了用于数据路径的纠错的动态切换组织。 动态切换组织包括用于发送数据信息和控制信息的数据路径以及沿数据路径具有多个输入和多个输出的交叉点交换结构。 交叉点交换结构具有耦合到仲裁总线的仲裁总线和交叉点交换板，使得板同步并行处理数据。 交叉点交换结构还包括用于将数据从一个输入引导到输出的特定一个的控制实体，并且数据包括数据位和校验位。 控制实体分布在交叉点交换板之间，使得每个板包括控制实体的一部分。 此外，交叉点交换结构包括用于对数据和校验位应用纠错方案（即汉明纠错方案）的纠错机制，使得纠错机制识别错误位并反转错误位以形成 校正数据。 通过添加允许检查方案是否正常工作的特征来提供对纠错方案的改进; 为了能够通过诊断软件进行检查，故意在特定数据位上引入错误。

    Clock compensation circuit
    10.
    发明授权
    Clock compensation circuit 失效

    公开(公告)号：US5838179A

    公开(公告)日：1998-11-17

    申请号：US798939

    申请日：1997-02-11

    申请人： Steven G. Schmidt

    发明人： Steven G. Schmidt

    IPC分类号： G06F1/10 ,  H03K5/13 ,  H03L7/06

    CPC分类号： G06F1/10 ,  H03K5/133

    摘要： A clock compensation circuit includes a clock tree; a reference clock; a phase detector for detecting relative phase information of the tree clock and the reference clock; a controller, coupled to said phase detector, for determining and controlling the amount of delay necessary to shift the output of the clock tree in phase with the reference clock; and a programmable delay logic coupled to said controller. The programmable delay logic comprises a string of delay elements that selectively participate in a delay string for shifting the tree clock in phase with the reference clock.