公开(公告)号：US08563389B2

公开(公告)日：2013-10-22

申请号：US13110693

申请日：2011-05-18

申请人： Harry-Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo ,  Bao-Ru Young

IPC分类号： H01L21/20

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： An embodiment of the disclosure includes a method of forming an integrated circuit. A substrate having an active region and a passive region is provided. A plurality of trenches is formed in the passive region. A root mean square of a length and a width of each trench is less than 5 μm. An isolation material is deposited over the substrate to fill the plurality of trenches. The isolation material is planarized to form a plurality of isolation structures. A plurality of silicon gate stacks and at least one silicon resistor stack are formed on the substrate in the active region and on the plurality of isolation structures respectively.

摘要翻译： 本公开的实施例包括形成集成电路的方法。 提供具有有源区和无源区的衬底。 在被动区域中形成多个沟槽。 每个沟槽的长度和宽度的均方根小于5um。 隔离材料沉积在衬底上以填充多个沟槽。 隔离材料被平坦化以形成多个隔离结构。 分别在有源区域和多个隔离结构上的衬底上形成多个硅栅叠层和至少一个硅电阻堆叠。

公开(公告)号：US20110220963A1

公开(公告)日：2011-09-15

申请号：US12720504

申请日：2010-03-09

申请人： Harry Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

发明人： Harry Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

IPC分类号： H01L27/06 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/28123 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/78

摘要： The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate. The transistor includes a collector region that is formed in a portion of the substrate. The transistor includes a base region that is surrounded by the collector region. The transistor includes an emitter region that is surrounded by the based region. The transistor includes an isolation structure that is disposed adjacent the emitter region. The transistor includes a gate structure that is disposed over a portion of the emitter region and a portion of the isolation structure.

摘要翻译： 本公开提供了具有晶体管的半导体器件。 晶体管包括衬底。 晶体管包括形成在基板的一部分中的集电极区域。 晶体管包括由集电极区域包围的基极区域。 晶体管包括由基于区域包围的发射极区域。 晶体管包括邻近发射极区设置的隔离结构。 晶体管包括设置在发射极区域的一部分和隔离结构的一部分上的栅极结构。

公开(公告)号：US20110215404A1

公开(公告)日：2011-09-08

申请号：US12719720

申请日：2010-03-08

申请人： Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang

发明人： Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L23/60

CPC分类号： H01L29/66484 ,  H01L21/8234 ,  H01L23/60 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides a semiconductor device having a transistor. The transistor includes a source region, a drain region, and a channel region that are formed in a semiconductor substrate. The channel region is disposed between the source and drain regions. The transistor includes a first gate that is disposed over the channel region. The transistor includes a plurality of second gates that are disposed over the drain region.

摘要翻译： 本公开提供了具有晶体管的半导体器件。 晶体管包括形成在半导体衬底中的源极区，漏极区和沟道区。 沟道区域设置在源区和漏区之间。 晶体管包括设置在沟道区域上的第一栅极。 晶体管包括设置在漏区上的多个第二栅极。

公开(公告)号：US20110156142A1

公开(公告)日：2011-06-30

申请号：US12647031

申请日：2009-12-24

申请人： Lee-Wee Teo ,  Ming Zhu ,  Harry Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0646 ,  H01L29/165 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.

摘要翻译： 提供一种半导体器件，其包括半导体衬底，形成在衬底上的栅极结构，形成在栅极结构的每一侧上的侧壁间隔物，形成在栅极结构的任一侧上的衬底中的源极和漏极，源极和 具有第一类型的导电性的漏极，形成在衬底中并与栅极结构的一侧对齐的轻掺杂区域，具有第一类型导电性的轻掺杂区域和形成在衬底中并邻近漏极的势垒区域。 阻挡区域通过掺杂不同于第一类型导电性的第二类型导电性的掺杂剂而形成。

公开(公告)号：US09196611B2

公开(公告)日：2015-11-24

申请号：US14250519

申请日：2014-04-11

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L31/119 ,  H01L27/06 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光刻胶（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US08378428B2

公开(公告)日：2013-02-19

申请号：US12893338

申请日：2010-09-29

申请人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82385 ,  H01L29/66545

摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.

摘要翻译： 应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

公开(公告)号：US08349678B2

公开(公告)日：2013-01-08

申请号：US12701824

申请日：2010-02-08

申请人： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

发明人： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate.

摘要翻译： 制造横向扩散的金属氧化物半导体（LDMOS）晶体管的方法包括在衬底上形成虚拟栅极。 在虚拟栅极的相对侧上的衬底上形成源极和漏极。 在源上形成第一硅化物。 在漏极上形成第二硅化物，使得至少一个漏极或源极的非硅化区域与虚拟栅极相邻。 漏极的非硅化区域提供能够承受适合于高电压LDMOS应用的电压负载的电阻区域。 在虚拟栅极上执行替换栅极处理以形成栅极。

公开(公告)号：US08304831B2

公开(公告)日：2012-11-06

申请号：US12701656

申请日：2010-02-08

申请人： Ming Zhu ,  Lee-Wee Teo ,  Han-Guan Chew ,  Harry Hak-Lay Chuang

发明人： Ming Zhu ,  Lee-Wee Teo ,  Han-Guan Chew ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66659

摘要： The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.

摘要翻译： 本公开提供了具有晶体管的半导体器件。 晶体管包括衬底以及设置在衬底内的第一和第二阱。 第一和第二阱掺杂不同类型的掺杂剂。 晶体管包括至少部分地设置在第一阱上的第一栅极。 晶体管还包括设置在第二阱上的第二栅极。 晶体管还包括源区和漏区。 源极和漏极区分别设置在第一和第二阱中。 源区和漏区掺杂有相同类型的掺杂剂。

公开(公告)号：US08143137B2

公开(公告)日：2012-03-27

申请号：US12706782

申请日：2010-02-17

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。

公开(公告)号：US20110227167A1

公开(公告)日：2011-09-22

申请号：US12724904

申请日：2010-03-16

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光刻胶（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。