公开(公告)号：US08378428B2

公开(公告)日：2013-02-19

申请号：US12893338

申请日：2010-09-29

申请人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82385 ,  H01L29/66545

摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.

摘要翻译： 应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

公开(公告)号：US08304840B2

公开(公告)日：2012-11-06

申请号：US12846261

申请日：2010-07-29

申请人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02 ,  H01L21/70 ,  H01L27/088

CPC分类号： H01L29/401 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088

摘要： The disclosure relates to spacer structures of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate having a first active region and a second active region; a plurality of first gate electrodes having a gate pitch over the first active region, wherein each first gate electrode has a first width; a plurality of first spacers adjoining the plurality of first gate electrodes, wherein each first spacer has a third width; a plurality of second gate electrodes having the same gate pitch as the plurality of first gate electrodes over the second active region, wherein each second gate electrode has a second width greater than the first width; and a plurality of second spacers adjoining the plurality of second gate electrodes, wherein each second spacer has a fourth width less than the third width.

摘要翻译： 本公开涉及半导体器件的间隔结构。 半导体器件的示例性结构包括具有第一有源区和第二有源区的衬底; 多个在所述第一有源区上具有栅间距的第一栅电极，其中每个第一栅电极具有第一宽度; 与所述多个第一栅电极相邻的多个第一间隔件，其中每个第一间隔件具有第三宽度; 多个第二栅电极，其具有与第二有源区上的多个第一栅电极相同的栅极间距，其中每个第二栅电极具有大于第一宽度的第二宽度; 以及与所述多个第二栅电极相邻的多个第二间隔件，其中每个第二间隔件具有小于所述第三宽度的第四宽度。

公开(公告)号：US08183644B1

公开(公告)日：2012-05-22

申请号：US13025956

申请日：2011-02-11

申请人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Bao-Ru Young ,  Ming Zhu ,  Hui-Wen Lin ,  Lee-Wee Teo

IPC分类号： H01L21/027

CPC分类号： H01L21/823842 ,  H01L21/823871

摘要： The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising a P-active region, an N-active region, and an isolation region interposed between the P- and N-active regions; a P-metal gate electrode over the P-active region, that extends over the isolation region; and an N-metal gate electrode having a first width over the N-active region, that extends over the isolation region and has a contact section in the isolation region electrically contacting the P-metal gate electrode, wherein the contact section has a second width greater than the first width.

摘要翻译： 本发明涉及集成电路制造，更具体地涉及一种金属栅极结构。 CMOS半导体器件的示例性结构包括：衬底，其包括P活性区域，N活性区域和插入在P-活性区域和N - 活性区域之间的隔离区域; 在P-活性区域上的P金属栅极电极，其在隔离区域上延伸; 以及在所述N-有源区上具有第一宽度的N-金属栅电极，其在所述隔离区上延伸，并且在所述隔离区中具有与所述P金属栅电极电接触的接触部，其中所述接触部具有第二宽度 大于第一宽度。

公开(公告)号：US20120025309A1

公开(公告)日：2012-02-02

申请号：US12846457

申请日：2010-07-29

申请人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/513 ,  H01L29/495

摘要： An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

摘要翻译： 偏移门半导体器件包括衬底和形成在衬底中的隔离特征。 在基板上基本上与隔离特征相邻地形成有源区。 在隔离特征和有源区上的衬底上形成界面层。 在隔离特征和有源区上的界面层上形成多晶硅层。 在隔离特征上形成在多晶硅层中的沟槽。 沟槽延伸到界面层。 形成填充层以在沟槽中形成沟槽和形成的金属栅极。

公开(公告)号：US08563389B2

公开(公告)日：2013-10-22

申请号：US13110693

申请日：2011-05-18

申请人： Harry-Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo ,  Bao-Ru Young

IPC分类号： H01L21/20

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： An embodiment of the disclosure includes a method of forming an integrated circuit. A substrate having an active region and a passive region is provided. A plurality of trenches is formed in the passive region. A root mean square of a length and a width of each trench is less than 5 μm. An isolation material is deposited over the substrate to fill the plurality of trenches. The isolation material is planarized to form a plurality of isolation structures. A plurality of silicon gate stacks and at least one silicon resistor stack are formed on the substrate in the active region and on the plurality of isolation structures respectively.

摘要翻译： 本公开的实施例包括形成集成电路的方法。 提供具有有源区和无源区的衬底。 在被动区域中形成多个沟槽。 每个沟槽的长度和宽度的均方根小于5um。 隔离材料沉积在衬底上以填充多个沟槽。 隔离材料被平坦化以形成多个隔离结构。 分别在有源区域和多个隔离结构上的衬底上形成多个硅栅叠层和至少一个硅电阻堆叠。

公开(公告)号：US08450216B2

公开(公告)日：2013-05-28

申请号：US12849601

申请日：2010-08-03

申请人： Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/302

CPC分类号： H01L29/66545 ,  H01L21/0217 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7833

摘要： An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.

摘要翻译： 根据至少一个实施例的用于场效应晶体管的示例性结构包括：包括表面的基板; 栅极结构，其包括在所述衬底上的侧壁和顶表面; 邻近所述栅极结构的侧壁的间隔物; 在所述间隔物上方的第一接触蚀刻停止层，并沿着所述衬底的表面延伸; 与所述第一接触蚀刻停止层相邻的层间电介质层，其中所述层间电介质层的顶表面与所述栅极结构的顶表面共面; 以及在栅极结构的顶表面上的第二接触蚀刻停止层。

公开(公告)号：US08258584B2

公开(公告)日：2012-09-04

申请号：US12846457

申请日：2010-07-29

申请人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

发明人： Chun-Hung Chen ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/513 ,  H01L29/495

摘要： An offset gate semiconductor device includes a substrate and an isolation feature formed in the substrate. An active region is formed in the substrate substantially adjacent to the isolation feature. An interface layer is formed on the substrate over the isolation feature and the active region. A polysilicon layer is formed on the interface layer over the isolation feature and the active region. A trench being formed in the polysilicon layer over the isolation feature. The trench extending to the interface layer. A fill layer is formed to line the trench and a metal gate formed in the trench.

摘要翻译： 偏移门半导体器件包括衬底和形成在衬底中的隔离特征。 在基板上基本上与隔离特征相邻地形成有源区。 在隔离特征和有源区上的衬底上形成界面层。 在隔离特征和有源区上的界面层上形成多晶硅层。 在隔离特征上形成在多晶硅层中的沟槽。 沟槽延伸到界面层。 形成填充层以在沟槽中形成沟槽和形成的金属栅极。

公开(公告)号：US08835294B2

公开(公告)日：2014-09-16

申请号：US12724984

申请日：2010-03-16

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/02697 ,  H01L21/3215 ,  H01L21/76825 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成栅极结构，所述栅极结构包括虚拟栅极，从栅极结构去除伪栅极，从而形成沟槽，形成工件 功能金属层部分地填充沟槽，形成填充沟槽的其余部分的填充金属层，执行化学机械抛光（CMP）以去除沟槽外部的金属层，并将Si，C或Ge注入剩余的 填充金属层的一部分。

公开(公告)号：US08697517B2

公开(公告)日：2014-04-15

申请号：US12724904

申请日：2010-03-16

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L21/8242

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光致抗蚀剂（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US08664079B2

公开(公告)日：2014-03-04

申请号：US13316817

申请日：2011-12-12

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。