公开(公告)号：US09196611B2

公开(公告)日：2015-11-24

申请号：US14250519

申请日：2014-04-11

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L31/119 ,  H01L27/06 ,  H01L23/522 ,  H01L27/02 ,  H01L27/08

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光刻胶（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US08378428B2

公开(公告)日：2013-02-19

申请号：US12893338

申请日：2010-09-29

申请人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Lee-Wee Teo ,  Ming Zhu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/02

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/82385 ,  H01L29/66545

摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.

摘要翻译： 应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

公开(公告)号：US08349678B2

公开(公告)日：2013-01-08

申请号：US12701824

申请日：2010-02-08

申请人： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

发明人： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate.

摘要翻译： 制造横向扩散的金属氧化物半导体（LDMOS）晶体管的方法包括在衬底上形成虚拟栅极。 在虚拟栅极的相对侧上的衬底上形成源极和漏极。 在源上形成第一硅化物。 在漏极上形成第二硅化物，使得至少一个漏极或源极的非硅化区域与虚拟栅极相邻。 漏极的非硅化区域提供能够承受适合于高电压LDMOS应用的电压负载的电阻区域。 在虚拟栅极上执行替换栅极处理以形成栅极。

公开(公告)号：US08304831B2

公开(公告)日：2012-11-06

申请号：US12701656

申请日：2010-02-08

申请人： Ming Zhu ,  Lee-Wee Teo ,  Han-Guan Chew ,  Harry Hak-Lay Chuang

发明人： Ming Zhu ,  Lee-Wee Teo ,  Han-Guan Chew ,  Harry Hak-Lay Chuang

IPC分类号： H01L29/66

CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66659

摘要： The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.

摘要翻译： 本公开提供了具有晶体管的半导体器件。 晶体管包括衬底以及设置在衬底内的第一和第二阱。 第一和第二阱掺杂不同类型的掺杂剂。 晶体管包括至少部分地设置在第一阱上的第一栅极。 晶体管还包括设置在第二阱上的第二栅极。 晶体管还包括源区和漏区。 源极和漏极区分别设置在第一和第二阱中。 源区和漏区掺杂有相同类型的掺杂剂。

公开(公告)号：US08143137B2

公开(公告)日：2012-03-27

申请号：US12706782

申请日：2010-02-17

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。

公开(公告)号：US20110227167A1

公开(公告)日：2011-09-22

申请号：US12724904

申请日：2010-03-16

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光刻胶（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US20110210403A1

公开(公告)日：2011-09-01

申请号：US12713395

申请日：2010-02-26

申请人： Lee-Wee TEO ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

发明人： Lee-Wee TEO ,  Ming Zhu ,  Chi-Ju Lee ,  Sheng-Chen Chung ,  Kai-Shyang You ,  Harry-Hak-Lay Chuang

IPC分类号： H01L29/78 ,  H01L21/768

CPC分类号： H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78

摘要： The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these neighboring devices. The metal gate under contact plugs that are adjacent to devices and share the (or are connected to) metal gate is defined and lined with a work function layer that has good step coverage to prevent contact metal from extruding into gate stacks of neighboring devices. Only modification to the mask layout for the photomask(s) used for removing dummy polysilicon is involved. No additional lithographical operation or mask is needed. Therefore, no modification to the manufacturing processes or additional substrate processing steps (or operations) is involved or required. The benefits of using the methods and structures described above may include increased device yield and performance.

摘要翻译： 所描述的方法和结构用于防止接触金属（例如W）水平地突出到相邻设备的门堆叠中，以影响这些相邻设备的功能。 定义了与设备相邻并且共享（或连接到）金属栅极的接触插塞下面的金属栅，并且衬有具有良好阶梯覆盖的功函数层，以防止接触金属挤出到相邻器件的栅极堆叠中。 仅涉及用于去除伪多晶硅的光掩模的掩模布局的修改。 不需要额外的光刻操作或掩模。 因此，不涉及制造工艺或附加的基板处理步骤（或操作）的修改。 使用上述方法和结构的好处可以包括提高器件产量和性能。

公开(公告)号：US08835294B2

公开(公告)日：2014-09-16

申请号：US12724984

申请日：2010-03-16

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry Hak-Lay Chuang ,  Yi-Ren Chen

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/02697 ,  H01L21/3215 ,  H01L21/76825 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底上形成栅极结构，所述栅极结构包括虚拟栅极，从栅极结构去除伪栅极，从而形成沟槽，形成工件 功能金属层部分地填充沟槽，形成填充沟槽的其余部分的填充金属层，执行化学机械抛光（CMP）以去除沟槽外部的金属层，并将Si，C或Ge注入剩余的 填充金属层的一部分。

公开(公告)号：US08697517B2

公开(公告)日：2014-04-15

申请号：US12724904

申请日：2010-03-16

申请人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

发明人： Harry Hak-Lay Chuang ,  Ming Zhu ,  Lee-Wee Teo

IPC分类号： H01L21/8242

CPC分类号： H01L27/0617 ,  H01L23/5227 ,  H01L27/0207 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.

摘要翻译： 本公开为半导体器件中的电感器提供了减少的衬底耦合。 制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。 该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。 该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光致抗蚀剂（PR）层。 然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以 形成在不包括金属栅极的第二区域上。

公开(公告)号：US08664079B2

公开(公告)日：2014-03-04

申请号：US13316817

申请日：2011-12-12

申请人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

发明人： Han-Guan Chew ,  Ming Zhu ,  Lee-Wee Teo ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/76

CPC分类号： H01L21/3081 ,  H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

摘要翻译： 本公开涉及集成电路制造，更具体地涉及一种用于制造半导体器件的方法。 用于制造半导体器件的示例性方法包括提供衬底; 在衬底的前侧和后侧形成衬垫氧化物层; 在衬底的前侧和后侧上的衬垫氧化物层上形成硬掩模层; 以及在衬底的前侧的衬垫氧化物层之上使硬掩模层变薄。