公开(公告)号：US08889501B2

公开(公告)日：2014-11-18

申请号：US13486240

申请日：2012-06-01

申请人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young ,  Yen-Ru Lee ,  Chii-Horng Li ,  Tze-Liang Lee

发明人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young ,  Yen-Ru Lee ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/11

CPC分类号： H01L27/1116 ,  H01L21/823807 ,  H01L21/823814

摘要： A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.

摘要翻译： 一种方法包括在半导体衬底上形成第一器件的第一栅极堆叠，以及在半导体衬底上形成第二MOS器件的第二栅极堆叠。 执行第一外延以形成用于第二MOS器件的源/漏应力源，其中源极/漏极应力器与第二栅极堆叠相邻。 执行第二外延以同时形成第一硅层和第二硅层，其中第一硅层位于半导体衬底的第一部分之上并且与第一栅极堆叠相邻。 第二硅层与源极/漏极应力源重叠。

公开(公告)号：US20130323893A1

公开(公告)日：2013-12-05

申请号：US13486240

申请日：2012-06-01

申请人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young ,  Yen-Ru Lee ,  Chii-Horng Li ,  Tze-Liang Lee

发明人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young ,  Yen-Ru Lee ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L21/8238

CPC分类号： H01L27/1116 ,  H01L21/823807 ,  H01L21/823814

摘要： A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.

摘要翻译： 一种方法包括在半导体衬底上形成第一器件的第一栅极堆叠，以及在半导体衬底上形成第二MOS器件的第二栅极堆叠。 执行第一外延以形成用于第二MOS器件的源/漏应力源，其中源极/漏极应力器与第二栅极堆叠相邻。 执行第二外延以同时形成第一硅层和第二硅层，其中第一硅层位于半导体衬底的第一部分之上并且与第一栅极堆叠相邻。 第二硅层与源极/漏极应力源重叠。

公开(公告)号：US09324622B2

公开(公告)日：2016-04-26

申请号：US13586472

申请日：2012-08-15

申请人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/324 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.

摘要翻译： 一种形成半导体器件的方法包括在衬底上形成栅极叠层，在邻近栅极叠层的边缘的衬底中形成非晶化区域，在衬底上形成应力膜，执行用pinchoff形成位错的过程 在衬底中去除至少一部分位错以在衬底中形成具有尖端的凹腔，并且在凹腔中形成源/漏特征。

公开(公告)号：US20140048886A1

公开(公告)日：2014-02-20

申请号：US13586472

申请日：2012-08-15

申请人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young

发明人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young

IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/324 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.

摘要翻译： 一种形成半导体器件的方法包括在衬底上形成栅极叠层，在邻近栅极叠层的边缘的衬底中形成非晶化区域，在衬底上形成应力膜，执行用pinchoff形成位错的工艺 在衬底中去除至少一部分位错以在衬底中形成具有尖端的凹腔，并且在凹腔中形成源/漏特征。

公开(公告)号：US20130154022A1

公开(公告)日：2013-06-20

申请号：US13331214

申请日：2011-12-20

申请人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

发明人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

摘要翻译： 一种方法包括形成PMOS器件。 该方法包括在半导体衬底和PMOS区域上形成栅极电介质层，在栅极电介质层和PMOS区域上形成第一含金属层，对PMOS区域中的第一含金属层进行处理 使用含氧处理气体，并在第一含金属层和PMOS区域上形成第二含金属层。 第二含金属层具有低于硅的中间间隙功函数的功函数。 第一含金属层和第二含金属层形成PMOS器件的栅极。

公开(公告)号：US09142414B2

公开(公告)日：2015-09-22

申请号：US13331214

申请日：2011-12-20

申请人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

发明人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

摘要翻译： 一种方法包括形成PMOS器件。 该方法包括在半导体衬底和PMOS区域上形成栅极电介质层，在栅极电介质层和PMOS区域上形成第一含金属层，对PMOS区域中的第一含金属层进行处理 使用含氧处理气体，并在第一含金属层和PMOS区域上形成第二含金属层。 第二含金属层具有低于硅的中间间隙功函数的功函数。 第一含金属层和第二含金属层形成PMOS器件的栅极。

公开(公告)号：US08343867B2

公开(公告)日：2013-01-01

申请号：US13234674

申请日：2011-09-16

申请人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/4763

CPC分类号： H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

摘要： The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

摘要翻译： 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层（或硬掩模）在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀（或修整）工艺的工艺均匀性（或控制）确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要，例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物，并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好，接触良好的硅化物提高了接触的收率，并使接触电阻达到可接受和可操作的范围。

公开(公告)号：US08039388B1

公开(公告)日：2011-10-18

申请号：US12730375

申请日：2010-03-24

申请人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

发明人： Jin-Aun Ng ,  Yu-Ying Hsu ,  Chi-Ju Lee ,  Sin-Hua Wu ,  Bao-Ru Young ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/4763

CPC分类号： H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

摘要： The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

摘要翻译： 在本公开中描述的用于修整用于替换栅极的氮化物间隔物的方法的实施例允许硬掩模层（或硬掩模）在修整回复工艺期间保护高K电介质上方的多晶硅。 工艺顺序还允许基于氮化物沉积和氮化物回蚀（或修整）工艺的工艺均匀性（或控制）确定修剪量。 氮化物间隔件后退工艺集成对于避免产生不期望的后果至关重要，例如上述高K电介质顶部的硅化聚异氰酸酯。 集成的过程还允许扩大栅极结构之间的空间以允许形成具有良好质量的硅化物，并允许接触插塞与硅化物区域充分接触。 接触插塞和硅化物区域之间质量好，接触良好的硅化物提高了接触的收率，并使接触电阻达到可接受和可操作的范围。