Information recording medium evaluation method, information recording medium, method for manufacturing information recording medium, signal processing method and access control apparatus
    1.
    发明授权
    Information recording medium evaluation method, information recording medium, method for manufacturing information recording medium, signal processing method and access control apparatus 有权
    信息记录介质评估方法,信息记录介质,信息记录介质的制造方法,信号处理方法和访问控制装置

    公开(公告)号:US08254234B2

    公开(公告)日:2012-08-28

    申请号:US13207570

    申请日:2011-08-11

    Abstract: A method for rating an information recording medium according to the present invention includes the steps of: receiving a digital read signal, which has been generated based on an analog read signal representing information that has been read from the information recording medium, and shaping the waveform of the digital read signal; subjecting the shaped digital read signal to maximum likelihood decoding, thereby generating a binarized signal showing a result of the maximum likelihood decoding; and calculating the quality of the digital read signal based on the shaped digital read signal and the binarized signal. If the quality of the read signal is calculated by a PRML method in which a number of zero-cross portions are included in a merging path of a minimum difference metric, the quality is calculated by using only a state transition pattern in which only one zero-cross portion is included in a merging path of a non-minimum difference metric.

    Abstract translation: 根据本发明的用于对信息记录介质进行评级的方法包括以下步骤:接收基于表示从信息记录介质读取的信息的模拟读取信号产生的数字读取信号,并且对波形进行整形 的数字读取信号; 对成形数字读取信号进行最大似然解码,从而生成表示最大似然解码结果的二值化信号; 并根据成形数字读取信号和二值化信号计算数字读取信号的质量。 如果通过PRML方法计算读取信号的质量,其中在最小差值度量的合并路径中包括多个零交叉部分,则仅通过仅使用一个零的状态转换模式来计算质量 - 交叉部分被包括在非最小差值度量的合并路径中。

    CLOCK SIGNAL GENERATION DEVICE
    4.
    发明申请
    CLOCK SIGNAL GENERATION DEVICE 审中-公开
    时钟信号发生装置

    公开(公告)号:US20100149940A1

    公开(公告)日:2010-06-17

    申请号:US12067902

    申请日:2006-09-27

    Abstract: A clock signal generator according to the present invention includes: a wobble phase error detecting section for detecting a wobble phase error that is a difference in phase between a wobble signal, representing a wobbled shape of a track on an optical disk medium, and a clock signal; a data phase error detecting section for detecting a data phase error that is a difference in phase between a data signal, representing data that has been written on the optical disk medium, and the clock signal; a frequency control section for generating a frequency control signal to control the frequency of the clock signal based on the wobble phase error and the data phase error; and a clock oscillation section for generating the clock signal with its frequency controlled in accordance with the frequency control signal.

    Abstract translation: 根据本发明的时钟信号发生器包括:摆动相位误差检测部分,用于检测作为表示光盘介质上的轨道的摆动形状的摆动信号与时钟之间的相位差的摆动相位误差 信号; 数据相位误差检测部分,用于检测表示已经写在光盘介质上的数据的数据信号与时钟信号之间的相位差的数据相位误差; 频率控制部分,用于基于摆动相位误差和数据相位误差产生频率控制信号以控制时钟信号的频率; 以及时钟振荡部分,用于产生其频率根据频率控制信号而被控制的时钟信号。

    Recording medium access device
    5.
    发明授权
    Recording medium access device 有权
    记录介质访问设备

    公开(公告)号:US08004945B2

    公开(公告)日:2011-08-23

    申请号:US12282439

    申请日:2007-03-13

    CPC classification number: G11B20/10009 G11B7/0053 G11B7/08523 G11B2220/2537

    Abstract: An information reproduction device according to the present invention is a device for accessing a recording medium having first address information and second address information recorded thereon. The first address information is represented by a shape formed on the recording medium in advance; and the second address information is recorded on the recording medium together with data. The information reproduction device includes a head section for accessing the recording medium to generate a reproduction signal; a first detection section for detecting the first address information from the reproduction signal; a second detection section for detecting the second address information from the reproduction signal; and a control section for, based on a detection result of either the first detection section or the second detection section which detected the address information first, controlling an access after the detection to the recording medium.

    Abstract translation: 根据本发明的信息再现装置是用于访问其上记录有第一地址信息和第二地址信息的记录介质的装置。 第一地址信息由形成在记录介质上的形状预先表示; 并且第二地址信息与数据一起被记录在记录介质上。 信息再现装置包括用于访问记录介质以产生再现信号的头部分; 第一检测部分,用于从再现信号中检测第一地址信息; 第二检测部分,用于从再现信号中检测第二地址信息; 以及控制部分,用于基于首先检测到地址信息的第一检测部分或第二检测部分的检测结果,控制检测到记录介质之后的访问。

    Optical disc, optical disc drive, optical disc recording/reproducing method, and integrated circuit
    6.
    发明授权
    Optical disc, optical disc drive, optical disc recording/reproducing method, and integrated circuit 有权
    光盘,光盘驱动器,光盘记录/再现方法和集成电路

    公开(公告)号:US07898933B2

    公开(公告)日:2011-03-01

    申请号:US12881338

    申请日:2010-09-14

    Abstract: A big pattern for a run-in area which allows data reproduction to be performed stably even when the recording density of an optical disc is increased is provided. An optical disc according to the present invention includes tracks, each of which divided into a plurality of recording blocks. Each of the plurality of blocks includes a run-in area and a data area. In the run-in area, a prescribed run-in bit pattern is recordable; and in the data area, bit patterns having a plurality of bit lengths obtained by modulating data as a recording target in accordance with a prescribed modulation rule are recordable. In this optical disc, at least one of spatial frequencies corresponding to the bit patterns having the plurality of bit lengths is higher than a cutoff frequency. The run-in bit pattern recordable in the run-in area includes the bit patterns having the plurality of bit lengths, from which the bit pattern corresponding to the frequency higher than the OTF cutoff frequency has been excluded.

    Abstract translation: 提供了即使当光盘的记录密度增加时也允许稳定地执行数据再现的运行区域的大图案。 根据本发明的光盘包括被分成多个记录块的轨道。 多个块中的每一个都包括导入区和数据区。 在跑步区域,可以记录规定的磨合位图案; 并且在数据区域中,可以记录具有根据规定的调制规则通过调制作为记录目标的数据而获得的多个位长度的位模式。 在该光盘中,对应于具有多个位长度的位模式的空间频率中的至少一个高于截止频率。 可以在导入区域中记录的流入位模式包括具有多个比特长度的比特模式,从而排除与高于OTF截止频率的频率对应的比特模式。

    Phase error detecting device, waveform shaping device and optical disc device
    7.
    发明授权
    Phase error detecting device, waveform shaping device and optical disc device 有权
    相位误差检测装置,波形整形装置和光盘装置

    公开(公告)号:US07869327B2

    公开(公告)日:2011-01-11

    申请号:US12343894

    申请日:2008-12-24

    Abstract: A waveform shaping portion receives a digital reproduced signal generated from an analog reproduced signal reproduced from an information recording medium and shapes the waveform of the digital reproduced signal. A maximum likelihood decoding portion applies maximum likelihood decoding to the digital reproduced signal in the shaped waveform and generates a binarized signal indicating the result of the maximum likelihood decoding. A phase detection portion extracts, during the maximum likelihood decoding, a phase error using state transition patterns having only a single zero cross point among differential metrics at a plurality of merging points at which a set of paths branched from a given state merges. A synchronization detection portion generates a reproduction clock signal using the phase error that has been detected and brings the digital reproduced signal into synchronization with the reproduction clock signal that has been generated. This configuration makes it possible to generate a reproduction clock signal in a stable manner.

    Abstract translation: 波形整形部分接收从信息记录介质再现的模拟再现信号产生的数字再生信号,并对数字再现信号的波形进行整形。 最大似然解码部分对成形波形中的数字再现信号应用最大似然解码,并生成指示最大似然解码结果的二值化信号。 相位检测部分在最大似然解码期间使用在从给定状态分支的一组路径合并的多个合并点处的差分度量中仅具有单个零交叉点的状态转换模式来提取相位误差。 同步检测部分使用已经检测到的相位误差来产生再现时钟信号,并使数字再现信号与已经产生的再现时钟信号同步。 该配置使得可以以稳定的方式产生再现时钟信号。

    Clock Signal Generation Device, Semiconductor Integrated Circuit, and Data Reproduction Method
    8.
    发明申请
    Clock Signal Generation Device, Semiconductor Integrated Circuit, and Data Reproduction Method 审中-公开
    时钟信号产生装置,半导体集成电路和数据再现方法

    公开(公告)号:US20080231332A1

    公开(公告)日:2008-09-25

    申请号:US10599237

    申请日:2005-03-23

    Abstract: The present invention improves a lead-in time of the PLL with a phase error detector having an enlarged range of phase error detection and gain control based on the PLL synchronous state. The phase error detection range is enlarged by correcting the phase error detection point in a case where the phase error increases. A locked state of the PLL is determined based on a standard deviation of the smoothed phase error values and the gains are switched between a lead-in transient state and a stationary state. As a result, it is possible to shorten and stabilize the lead-in time of the PLL.

    Abstract translation: 本发明利用具有基于PLL同步状态的相位误差检测和增益控制的扩大范围的相位误差检测器来改进PLL的导入时间。 在相位误差增大的情况下通过校正相位误差检测点来扩大相位误差检测范围。 PLL的锁定状态基于平滑相位误差值的标准偏差来确定,并且增益在导入瞬态和静止状态之间切换。 结果,可以缩短和稳定PLL的导入时间。

    INFORMATION RECORDING MEDIUM EVALUATION METHOD, INFORMATION RECORDING MEDIUM, METHOD FOR MANUFACTURING INFORMATION RECORDING MEDIUM, SIGNAL PROCESSING METHOD AND ACCESS CONTROL APPARATUS
    9.
    发明申请
    INFORMATION RECORDING MEDIUM EVALUATION METHOD, INFORMATION RECORDING MEDIUM, METHOD FOR MANUFACTURING INFORMATION RECORDING MEDIUM, SIGNAL PROCESSING METHOD AND ACCESS CONTROL APPARATUS 审中-公开
    信息记录介质评估方法,信息记录介质,制造信息记录介质的方法,信号处理方法和访问控制装置

    公开(公告)号:US20110032809A1

    公开(公告)日:2011-02-10

    申请号:US12910091

    申请日:2010-10-22

    Abstract: A method for rating an information recording medium according to the present invention includes the steps of: receiving a digital read signal, which has been generated based on an analog read signal representing information that has been read from the information recording medium, and shaping the waveform of the digital read signal; subjecting the shaped digital read signal to maximum likelihood decoding, thereby generating a binarized signal showing a result of the maximum likelihood decoding; and calculating the quality of the digital read signal based on the shaped digital read signal and the binarized signal. If the quality of the read signal is calculated by a PRML method in which a number of zero-cross portions are included in a merging path of a minimum difference metric, the quality is calculated by using only a state transition pattern in which only one zero-cross portion is included in a merging path of a non-minimum difference metric.

    Abstract translation: 根据本发明的用于对信息记录介质进行评级的方法包括以下步骤:接收基于表示从信息记录介质读取的信息的模拟读取信号产生的数字读取信号,并且对波形进行整形 的数字读取信号; 对成形数字读取信号进行最大似然解码,从而生成表示最大似然解码结果的二值化信号; 并根据成形数字读取信号和二值化信号计算数字读取信号的质量。 如果通过PRML方法计算读取信号的质量,其中在最小差值度量的合并路径中包括多个零交叉部分,则仅通过仅使用仅一个零的状态转换模式来计算质量 - 交叉部分被包括在非最小差值度量的合并路径中。

    Integrated circuit monitoring an internal signal converted from an analog input signal
    10.
    发明授权
    Integrated circuit monitoring an internal signal converted from an analog input signal 有权
    集成电路监控从模拟输入信号转换的内部信号

    公开(公告)号:US07584315B2

    公开(公告)日:2009-09-01

    申请号:US10818568

    申请日:2004-04-06

    CPC classification number: G01R31/3177

    Abstract: An integrated circuit includes: a signal processor, which receives an input signal and generates a processed signal, representing processing information obtained by subjecting the input signal to predetermined processing, and at least one type of internal signal including internal information obtained during the processing; at least one memory storing the processing information; an interface exchanges signals with an external device; and a controller controlling the signal processor, memory and interface. On receiving a first instruction from the external device through the interface, the controller controls the signal processor and memory such that the processing information is once stored in the memory and then output to the external device via the interface. In response to a second instruction, the controller controls the signal processor and memory such that the internal information is once stored in the memory and then output to the external device via the interface.

    Abstract translation: 集成电路包括:信号处理器,其接收输入信号并产生经处理的信号,表示通过对输入信号进行预定处理而获得的处理信息;以及至少一种内部信号,包括在处理期间获得的内部信息; 存储所述处理信息的至少一个存储器; 接口与外部设备交换信号; 以及控制信号处理器,存储器和接口的控制器。 在通过接口从外部设备接收到第一指令时,控制器控制信号处理器和存储器,使得处理信息曾经存储在存储器中,然后经由接口输出到外部设备。 响应于第二指令,控制器控制信号处理器和存储器,使得内部信息被一次存储在存储器中,然后经由接口输出到外部设备。

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