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公开(公告)号：US08174884B2
公开(公告)日：2012-05-08
申请号：US12804395
申请日：2010-07-20
IPC分类号： G11C11/34
CPC分类号： G11C16/0441
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider (804) is coupled in series with the switch. A sense transistor (152) has a sense control terminal (156) and a current path coupled between an output terminal (108) and a reference terminal (110). A first capacitor (154) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor (716) has a control terminal coupled to receive a read signal (721), and a current path coupled between the output terminal and a bit line (718).
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公开(公告)号：US20120020162A1
公开(公告)日：2012-01-26
申请号：US12804395
申请日：2010-07-20
CPC分类号： G11C16/0441
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider (804) is coupled in series with the switch. A sense transistor (152) has a sense control terminal (156) and a current path coupled between an output terminal (108) and a reference terminal (110). A first capacitor (154) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor (716) has a control terminal coupled to receive a read signal (721), and a current path coupled between the output terminal and a bit line (718).
摘要翻译： 公开了一种电可擦除可编程只读存储器（EEPROM）存储器阵列（图7和8）。 存储器阵列包括以行和列排列的多个存储单元。 每个存储单元具有耦合以接收第一编程电压（PGMDATA）和第一选择信号（ROWSEL）的开关（806）。 分压器（804）与开关串联耦合。 感测晶体管（152）具有感测控制端子（156）和耦合在输出端子（108）和参考端子（110）之间的电流通路。 第一电容器（154）具有耦合到开关的第一端子和耦合到感测控制端子的第二端子。 存取晶体管（716）具有耦合以接收读取信号（721）的控制端和耦合在输出端和位线（718）之间的电流通路。
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3.发明授权公开(公告)号：US08908412B2
公开(公告)日：2014-12-09
申请号：US12804439
申请日：2010-07-20
CPC分类号： G11C16/0441
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead (706) is connected to the switch of each memory cell in a first column. A bit line (718) is connected to the current path of each access transistor in the first column. A read select lead (721) is connected to a control terminal of each access transistor in the first row. A first row select lead (700) is connected to a control terminal of the switch in each memory cell in a first row.
摘要翻译： 公开了电可擦除可编程只读存储器（EEPROM）存储器阵列（图7）。 存储器阵列包括以行和列排列的多个存储单元。 每个存储单元具有开关（714），存取晶体管（716）和感测晶体管（720）。 每个存取晶体管的电流路径与每个相应感测晶体管的电流路径串联连接。 第一程序数据引线（706）连接到第一列中的每个存储器单元的开关。 位线（718）连接到第一列中每个存取晶体管的电流路径。 读取选择引线（721）连接到第一行中的每个存取晶体管的控制端子。 第一行选择引线（700）连接到第一行中的每个存储单元中的开关的控制端子。
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4.发明申请公开(公告)号：US20120020163A1
公开(公告)日：2012-01-26
申请号：US12804439
申请日：2010-07-20
IPC分类号： G11C16/04
CPC分类号： G11C16/0441
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead (706) is connected to the switch of each memory cell in a first column. A bit line (718) is connected to the current path of each access transistor in the first column. A read select lead (721) is connected to a control terminal of each access transistor in the first row. A first row select lead (700) is connected to a control terminal of the switch in each memory cell in a first row.
摘要翻译： 公开了电可擦除可编程只读存储器（EEPROM）存储器阵列（图7）。 存储器阵列包括以行和列排列的多个存储单元。 每个存储单元具有开关（714），存取晶体管（716）和感测晶体管（720）。 每个存取晶体管的电流路径与每个相应感测晶体管的电流路径串联连接。 第一程序数据引线（706）连接到第一列中的每个存储器单元的开关。 位线（718）连接到第一列中每个存取晶体管的电流路径。 读取选择引线（721）连接到第一行中的每个存取晶体管的控制端子。 第一行选择引线（700）连接到第一行中的每个存储单元中的开关的控制端子。
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公开(公告)号：US20100039868A1
公开(公告)日：2010-02-18
申请号：US12462076
申请日：2009-07-28
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： H01L27/11521 , G11C16/0416 , G11C2216/10 , H01L27/11558 , H01L29/42324 , H01L29/7883
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell (FIGS. 1-2) is disclosed. The memory cell includes a sense transistor (152) having a source (110), a drain (108), and a control gate layer (156). The memory cell includes a first lightly doped region (160) having a first conductivity type and a second lightly doped region (162) having the first conductivity type. A first dielectric region is formed between the control gate layer and the first lightly doped region. A second dielectric region is formed between the control gate layer and the second lightly doped region.
摘要翻译： 公开了电可擦除可编程只读存储器（EEPROM）存储单元（图1-2）。 存储单元包括具有源极（110），漏极（108）和控制栅极层（156）的检测晶体管（152）。 存储单元包括具有第一导电类型的第一轻掺杂区域（160）和具有第一导电类型的第二轻掺杂区域（162）。 在控制栅极层和第一轻掺杂区域之间形成第一电介质区域。 在控制栅极层和第二轻掺杂区域之间形成第二介电区域。
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公开(公告)号：US08716083B2
公开(公告)日：2014-05-06
申请号：US13359253
申请日：2012-01-26
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/0805 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.
摘要翻译： 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且分别包括用作n沟道和p沟道MOS晶体管的栅电极的n型和p型掺杂部分。 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。 在模拟浮栅电极的表面处，在浮栅电极的n型和p型掺杂部分邻接的位置处的开口允许在该位置形成硅化物，使p-n结短路。
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7.发明申请Analog Floating-Gate Memory Manufacturing Process Implementing N-Channel and P-Channel MOS Transistors 有权模拟浮栅存储器制造工艺实现N沟道和P沟道MOS晶体管公开(公告)号：US20130221418A1
公开(公告)日：2013-08-29
申请号：US13406704
申请日：2012-02-28
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L29/66825 , H01L21/2652 , H01L23/5223 , H01L27/11517 , H01L27/1156 , H01L28/40 , H01L28/60 , H01L29/105 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
摘要翻译： 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。
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公开(公告)号：US20130043934A1
公开(公告)日：2013-02-21
申请号：US13199002
申请日：2011-08-17
IPC分类号： H03F3/45 , H03K17/693 , G05F3/02
CPC分类号： H03F3/45475 , H03F2203/45546 , H03F2203/45548
摘要： An analog floating gate circuit (10-3, 10-4) includes a first sense transistor (21, 3), a first storage capacitor (20, 5), and first (24, 4) and second (31A, 42) tunneling regions. Various portions of a first floating gate conductor (12, 2) form a floating gate of the first sense transistor, a floating first plate of the first storage capacitor (20, 5), a floating first plate of the first tunneling region, and a floating first plate of the second tunneling region, respectively. A second plate of the first storage capacitor is coupled to a first reference voltage (VREF, GND), and a second plate of the second tunneling region is coupled to a second reference voltage (VPROG/GND). Compensation circuitry (44-1, 44-2) is coupled to the first floating gate conductor, for compensating loss of trapped charge from the first floating gate conductor.
摘要翻译： 模拟浮动栅极电路（10-3,10-4）包括第一检测晶体管（21,3），第一存储电容器（20,5）和第一（24,4）和第二（31A，42）隧道 地区。 第一浮栅导体（12,2）的各部分形成第一检测晶体管的浮置栅极，第一存储电容器（20,5）的浮置第一板，第一隧穿区域的浮置第一板，以及第 分别是第二隧道区的浮动第一板。 第一存储电容器的第二板耦合到第一参考电压（VREF，GND），并且第二隧穿区域的第二板耦合到第二参考电压（VPROG / GND）。 补偿电路（44-1,44-2）耦合到第一浮栅导体，用于补偿来自第一浮栅导体的俘获电荷损失。
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公开(公告)号：US20120244671A1
公开(公告)日：2012-09-27
申请号：US13359253
申请日：2012-01-26
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/0805 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.
摘要翻译： 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且分别包括用作n沟道和p沟道MOS晶体管的栅电极的n型和p型掺杂部分。 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。 在模拟浮栅电极的表面处，在浮栅电极的n型和p型掺杂部分邻接的位置处的开口允许在该位置形成硅化物，使p-n结短路。
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10.发明授权
公开(公告)号：US5143860A
公开(公告)日：1992-09-01
申请号：US686734
申请日：1991-04-17
IPC分类号： G11C11/56 , G11C16/04 , H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , G11C11/5621 , G11C11/5642 , G11C16/0458 , G11C16/0475 , H01L21/2815 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/7885 , H01L29/7887 , G11C2211/5612
摘要： An EPROM memory having sidewall floating gates (30) is disclosed. Sidewall floating gates (30) are formed on sidewalls (28) of field insulators (24). Spaced apart bit lines (22), which serve as memory cell sources and drains, are formed. The field insulators (24) overlie the bit lines (22), and sidewall floating gates are formed on the sidewalls (28) of the field insulators (24). In one embodiment, a second set of bit lines (36) is formed between the sidewall floating gates (30), and each memory cell contains one sidewall floating gate (30). In another embodiment, each memory cell contains two sidewall floating gate (30), and the memory cell may be programmed to store from two to four distinct information states.
摘要翻译： 公开了具有侧壁浮动门（30）的EPROM存储器。 侧壁浮动栅极（30）形成在场绝缘体（24）的侧壁（28）上。 形成用作存储单元源和漏极的间隔开的位线（22）。 场绝缘体（24）覆盖位线（22），并且侧壁浮动栅极形成在场绝缘体（24）的侧壁（28）上。 在一个实施例中，第二组位线（36）形成在侧壁浮动栅极（30）之间，并且每个存储器单元包含一个侧壁浮动栅极（30）。 在另一个实施例中，每个存储器单元包含两个侧壁浮动栅极（30），并且存储器单元可以被编程为从两个到四个不同的信息状态存储。
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