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公开(公告)号：US07624289B2
公开(公告)日：2009-11-24
申请号：US11949129
申请日：2007-12-03
CPC分类号： H01L23/50 , H01H59/0009 , H01L2924/0002 , H01L2924/3011 , Y10T307/469 , H01L2924/00
摘要： A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.
摘要翻译： 提供了一种用于集成电路芯片复合体的网络配电的结构和方法。 芯片复合体具有至少两个扇区，每个扇区具有至少一个功率提供与至少一个所述连接体的连接，所述至少一个所述连接体可以由给定的电源单独寻址并且可与其隔离。 至少一个MEMS被定位成选择性地将所述至少一个连接与所述给定电源连接和断开。
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公开(公告)号：US07305571B2
公开(公告)日：2007-12-04
申请号：US10940543
申请日：2004-09-14
CPC分类号： H01L23/50 , H01H59/0009 , H01L2924/0002 , H01L2924/3011 , Y10T307/469 , H01L2924/00
摘要： A structure and method for power distribution to a network for an integrated circuit chip complex are provided. The chip complex has at least two sectors, each having at least one power providing connection with at least one of said connections beings individually addressable by, and isolatable from, a given power source. At least one MEMS is positioned to selectively connect and disconnect said at least one connection to and from said given power source.
摘要翻译： 提供了一种用于集成电路芯片复合体的网络配电的结构和方法。 芯片复合体具有至少两个扇区，每个扇区具有至少一个功率提供与至少一个所述连接体的连接，所述至少一个所述连接体可以由给定的电源单独寻址并且可与其隔离。 至少一个MEMS被定位成选择性地将所述至少一个连接与所述给定电源连接和断开。
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公开(公告)号：US07719302B2
公开(公告)日：2010-05-18
申请号：US12215732
申请日：2008-06-30
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.
摘要翻译： 提供了一种用于监测半导体芯片组件内的互连电阻的方法。半导体芯片组件可以包括具有在半导体芯片的表面处露出的触点的半导体芯片和具有与触点导电连通的露出端子的基板。 半导体芯片的多个受监测元件可以包括导电互连，每个导体互连通过半导体芯片内的布线互连半导体芯片的相应的一对节点。 在这种方法的示例中，在半导体芯片组件的寿命期间，跨越每个被监测元件的电压降与在半导体芯片上的相应参考元件上的参考电压降在多个不同时间进行比较。 以这种方式，当这种被监视的元件的电阻超过阈值时，可以检测它。 基于这种比较的结果，可以做出是否指示动作条件的决定。
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公开(公告)号：US07840916B2
公开(公告)日：2010-11-23
申请号：US11985966
申请日：2007-11-19
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G01R31/2858
摘要： A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for example, a resistive voltage divider circuit operable to output a plurality of reference voltages having different values. A plurality of comparators in the semiconductor chip may be coupled to receive the reference voltages and a monitored voltage representative of a resistance of the monitored element. Each of the comparators may produce an output indicating whether the monitored voltage exceeds the reference voltages, so that the resistance value of the monitored element may be precisely determined.
摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构可以包括半导体芯片的装置，其可操作以检测半导体芯片的被监测元件的电阻的增加。 该设计结构可以包括例如可操作以输出具有不同值的多个参考电压的电阻分压器电路。 可以将半导体芯片中的多个比较器耦合以接收参考电压和表示所监视元件的电阻的监视电压。 每个比较器可以产生指示监视的电压是否超过参考电压的输出，使得可以精确地确定被监视元件的电阻值。
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公开(公告)号：US07394273B2
公开(公告)日：2008-07-01
申请号：US11306985
申请日：2006-01-18
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.
摘要翻译： 提供一种封装的半导体芯片，其包括半导体芯片和封装元件。 半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。 封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。 半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。 半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时 被监测元件的电阻超过阈值。
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6.发明授权One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效单采样每位决策反馈均衡器（DFE）时钟和数据恢复公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译： 公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。 集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。 输入电压被转换为电流并连接到电流求和节点。 由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。 另外，总和电流被积分并转换成电压。 采样器用于基于所得到的电压进行位决定。 采样后，积分器在分析下一位之前被复位。 通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。
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7.发明授权公开(公告)号：US07755420B2
公开(公告)日：2010-07-13
申请号：US12196718
申请日：2008-08-22
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译： 用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。 模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。 控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。
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8.发明授权公开(公告)号：US07721134B2
公开(公告)日：2010-05-18
申请号：US11566576
申请日：2006-12-04
CPC分类号： G01R31/3171 , B82Y25/00 , G01R33/093
摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.
摘要翻译： 提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。 接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘采样，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对 到数据采样时钟。 接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。 该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。 边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。
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公开(公告)号：US07684478B2
公开(公告)日：2010-03-23
申请号：US11427831
申请日：2006-06-30
CPC分类号： G01R31/31711 , H04L1/205 , H04L1/24
摘要： A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.
摘要翻译： 通过在具有未知周期TS的IC上以嵌入的采样时钟采样，数字化和存储数据信号的电压采样来生成发送数据信号的K个电压样本的序列。 K电压样本相对于K次顺序TB [K]的时基绘制，归一化，所以所有采样都落在用于生成数据信号的数据时钟或单位时间为1的一个周期内。时基是通过估计 采样时钟周期TSE为1 / P的某个倍数，其中P大于K.眼图分析时间抖动，其中只保存抖动的最小值。 TSE递增1 / P，直到TS大于数据时钟周期的一半。 TSE具有最小时间抖动的眼图用于分析数据通道。
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公开(公告)号：US07661052B2
公开(公告)日：2010-02-09
申请号：US12021950
申请日：2008-01-29
IPC分类号： G06F11/277 , G06F11/16
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
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