公开(公告)号：US20050191549A1

公开(公告)日：2005-09-01

申请号：US11044757

申请日：2005-01-27

申请人： Hee Kang ,  Hyang Lee ,  Oh Hyun ,  Chang Ahn ,  Sung-Min Hwang

发明人： Hee Kang ,  Hyang Lee ,  Oh Hyun ,  Chang Ahn ,  Sung-Min Hwang

IPC分类号： H01M2/02 ,  H01M2/08 ,  H01M2/30 ,  H01M10/04 ,  H01M10/05 ,  H01M10/0585 ,  H01M10/0587 ,  H01M10/38 ,  H01M10/42

CPC分类号： H01M2/021 ,  H01M10/04 ,  H01M10/058 ,  H01M10/425

摘要： The present invention provides a battery having a structure for increasing the power storage capacity and output thereof In accordance with the present invention, in a battery comprising an electrode assembly including anode plates, cathode plates and separators; and a battery case, both side bonding portions of which are folded toward adjacent sides thereof, for accommodating the electrode assembly and a designated amount of electrolyte, and sealing the electrode assembly such that two electrode terminals connected to corresponding electrode taps of the anode and cathode plates of the electrode assembly are exposed to the outside, an upper bonding portion of the battery case is folded toward the upper end of the battery case, and/or common portions of the upper bonding portion and both side portions of the battery case are cut off, and/or inner corners corresponding to the upper bonding portion have larger radiuses of curvature, and/or receipt portions for receiving the electrode assembly are respectively formed in upper and lower bodies of the battery case. The battery having the above structure has high power storage capacity and output at the same size of the battery package, and high sealing capacity and safety.

摘要翻译： 本发明提供一种具有增加蓄电能力和输出结构的电池。根据本发明，在包括阳极板，阴极板和隔板的电极组件的电池中， 以及电池壳体，其两侧接合部分朝向其相邻侧面折叠，用于容纳电极组件和指定量的电解质，并且密封电极组件，使得连接到阳极和阴极的相应电极抽头的两个电极端子 电极组件的板暴露于外部，电池壳体的上接合部分朝向电池壳体的上端折叠，和/或电池壳体的上接合部分和两侧部分的共同部分被切割 和/或对应于上部接合部分的内角具有较大的曲率半径，和/或用于接收电极组件的接收部分别形成在电池壳体的上部和下部主体中。 具有上述结构的电池具有高的蓄电容量和与电池组件相同尺寸的输出，并且具有高密封能力和安全性。

公开(公告)号：US20050123827A1

公开(公告)日：2005-06-09

申请号：US10992800

申请日：2004-11-19

申请人： Hee Kang ,  Oh Hyun ,  Chang Ahn ,  Hyang Lee

发明人： Hee Kang ,  Oh Hyun ,  Chang Ahn ,  Hyang Lee

IPC分类号： H01M4/13 ,  H01M10/04 ,  H01M10/05 ,  H01M10/0525 ,  H01M10/0585 ,  H01M4/02 ,  H01M6/42

CPC分类号： H01M4/0404 ,  H01M4/04 ,  H01M4/70 ,  H01M10/04 ,  H01M10/0413 ,  H01M10/0525 ,  H01M10/0585 ,  H01M10/38 ,  H01M10/4235

摘要： Provided is a cell wherein out of electrodes constituting the cell, the outermost two electrodes are both cathodes, cathode current collectors of the cathodes are single-side coated with cathode active materials on the first surfaces thereof, other sides of cathode current collectors non-coated with cathode active materials are disposed toward the outside of a cell assembly and the thickness of cathode current collectors is 70 to 150% of that of the cathode active material coated layer. The cell in accordance with the present invention exhibits excellent safety in a nail penetration test.

摘要翻译： 提供一种单元，其中，构成单元的电极中，最外面的两个电极都是阴极，阴极的阴极集电体在其第一表面上单面涂覆有阴极活性材料，阴极集电体的另一侧未涂覆 阴极活性物质朝向电池组件的外侧设置，阴极集电体的厚度为正极活性物质涂层的厚度的70〜150％。 根据本发明的细胞在指甲穿透试验中表现出优异的安全性。

公开(公告)号：US20070170481A1

公开(公告)日：2007-07-26

申请号：US11717145

申请日：2007-03-13

申请人： Hee Kang ,  Jin Ahn ,  Jae Lee

发明人： Hee Kang ,  Jin Ahn ,  Jae Lee

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L21/84 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7841

摘要： A nonvolatile ferroelectric memory device is provided so as to control read/write operations of a nonvolatile memory cell using a channel resistance of the memory cell which is differentiated by polarity states of a ferroelectric material. In the memory device, an insulating layer is formed on a bottom word line, and a floating channel layer comprising a N-type drain region, a P-type channel region and a N-type source region is formed on the insulating layer. Then, a ferroelectric layer is formed on the floating channel layer, and a word line is formed on the ferroelectric layer. As a result, the resistance state induced to the channel region is controlled depending on the polarity of the ferroelectric layer, thereby regulating the read/write operations of the memory cell array.

摘要翻译： 提供非易失性铁电存储器件，以便使用由铁电材料的极性状态区分的存储单元的沟道电阻来控制非易失性存储单元的读/写操作。 在存储器件中，在底部字线上形成绝缘层，并且在绝缘层上形成包括N型漏极区，P型沟道区和N型源极区的浮动沟道层。 然后，在浮动沟道层上形成铁电体层，在铁电体层上形成字线。 结果，根据铁电层的极性来控制感应到沟道区的电阻状态，从而调节存储单元阵列的读/写操作。

公开(公告)号：US20070090413A1

公开(公告)日：2007-04-26

申请号：US11482128

申请日：2006-07-07

申请人： Hee Kang ,  Jin Ahn

发明人： Hee Kang ,  Jin Ahn

IPC分类号： H01L29/768

CPC分类号： G11C11/22 ,  H01L27/11502 ,  H01L28/55

摘要： A nonvolatile ferroelectric memory device has a plurality of ferroelectric memory cells. The ferroelectric memory cells include a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the floating channel layer corresponding to the bit of datum stored in the first double gate cell; and a second double gate cell selectively turned on by a potential on a selection line to supply a potential of a sense line to the first double gate cell to control read and write operations of the first double gate cell. The present invention also provides methods for operating the nonvolatile ferroelectric memory device.

摘要翻译： 非易失性铁电存储器件具有多个铁电存储单元。 铁电存储单元包括用于存储一比特数据的第一双栅极单元，第一双栅极单元包括铁电层和浮动沟道层，其中，强电介质层的极性状态影响浮动沟道层的电阻， 对应于存储在第一双门单元中的基准的位的浮动通道层的电阻; 并且通过选择线上的电位选择性地导通第二双栅电池，以将感测线的电位提供给第一双栅极单元，以控制第一双栅极单元的读和写操作。 本发明还提供了用于操作非易失性铁电存储器件的方法。

公开(公告)号：US20070019460A1

公开(公告)日：2007-01-25

申请号：US11325351

申请日：2006-01-05

申请人： Hee Kang ,  Jin Ahn

发明人： Hee Kang ,  Jin Ahn

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A nonvolatile latch circuit and a system on a chip with the same feature detection of change of latch data in an active period to store new data in a latch without an additional data storage time. The nonvolatile latch circuit does not require an additional data storage period but detects change of latch data in the active period to store new data in a nonvolatile latch unit. When power is accidentally off, new data are constantly stored in the nonvolatile latch unit, thereby preventing data loss and improving an operating speed without a booting time for restoring data.

摘要翻译： 一种非易失性锁存电路和芯片上的系统，具有相同的特征检测在活动期间锁存数据的变化，以将新数据存储在锁存器中，而不需要额外的数据存储时间。 非易失性锁存电路不需要额外的数据存储周期，而是在活动期间检测锁存数据的变化，以将新数据存储在非易失性锁存单元中。 当电源意外关闭时，新数据不断存储在非易失性锁存单元中，从而防止数据丢失，提高运行速度，而无需启动恢复数据的时间。

公开(公告)号：US20060279690A1

公开(公告)日：2006-12-14

申请号：US11212042

申请日：2005-08-19

申请人： Sang Yu ,  Sang Han ,  Hee Kang ,  Kyo Choo

发明人： Sang Yu ,  Sang Han ,  Hee Kang ,  Kyo Choo

IPC分类号： G02F1/13

CPC分类号： H04N1/00129 ,  G02F1/13338 ,  G02F1/1362 ,  G02F2001/13312 ,  H04N1/00127 ,  H04N1/195 ,  H04N2201/0081

摘要： A liquid crystal display device includes a gate line and a data line intersecting each other on a substrate. The liquid crystal display device further includes a photo sensing device and a first thin film transistor (“TFT”) located at an intersection area of the gate line. The photo sensing device operates to sense an ambient light and includes a storage capacitor to store charge generated by light. The photo sensing device is drive by a driving voltage other than the data voltage.

公开(公告)号：US20060268606A1

公开(公告)日：2006-11-30

申请号：US11500974

申请日：2006-08-09

申请人： Hee Kang

发明人： Hee Kang

IPC分类号： G11C11/36

CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/72 ,  G11C2213/74

摘要： The present invention discloses a nano tube cell, and a semiconductor device having the nano tube cell and a double bit line sensing structure. The cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word line driving unit. Especially, the top and bottom sub cell arrays have a double bit line sensing structure for inducing a sensing voltage of a main bit line by controlling a volume of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data. Each of the sub cell arrays includes a capacitor, and a PNPN nano tube cell having a PNPN diode switch selectively turned on/off according to a voltage difference between one side terminal of the capacitor and the sub bit line, to decrease a cell size and improve operational characteristics of the circuit.

摘要翻译： 本发明公开了一种纳米管电池，以及具有纳米管电池和双位线感测结构的半导体器件。 单元阵列电路包括多个顶部子单元阵列，多个底部子单元阵列，主位线检测放大器和字线驱动单元。 特别地，顶部和底部子单元阵列具有双位线检测结构，用于通过根据电位检测电压控制从电源电压向主位线提供的电流的体积来感应主位线的感测电压 子位线接收单元数据。 每个子电池阵列包括电容器，并且具有根据电容器的一侧端子与子位线之间的电压差选择性地导通/截止的PNPN二极管开关的PNPN纳米管电池，以减小电池尺寸，以及 提高电路的运行特性。

公开(公告)号：US20060254514A1

公开(公告)日：2006-11-16

申请号：US11413927

申请日：2006-04-28

申请人： Hee Kang ,  Kazuo Furuno ,  Han Kim ,  Myoung Kim

发明人： Hee Kang ,  Kazuo Furuno ,  Han Kim ,  Myoung Kim

IPC分类号： C23C16/00

CPC分类号： C23C16/44 ,  C23C16/4408 ,  C23C16/455

摘要： A catalyst enhanced chemical vapor deposition (CECVD) apparatus is provided in which the showerhead and catalyst support are separated from each other. The CECVD apparatus has excellent spacing between the showerhead, catalyst wire and substrate and can be purged to prevent contaminants from forming on parts functioning at low temperatures. The CECVD apparatus comprises a reaction chamber, a showerhead for introducing reaction gas into the reaction chamber, a catalyst wire for decomposing the reaction gas, a catalyst support for supporting the catalyst wire, a substrate on which the decomposed gas is deposited, and a substrate support for supporting the substrate.

摘要翻译： 提供催化剂增强化学气相沉积（CECVD）装置，其中喷头和催化剂载体彼此分离。 CECVD装置在喷头，催化剂丝和基材之间具有优异的间距，并且可以被清除以防止在低温下起作用的部件上形成污染物。 CECVD装置包括反应室，用于将反应气体引入反应室的喷头，用于分解反应气体的催化剂丝，用于负载催化剂丝的催化剂载体，沉积有分解气体的基板和基板 支持底物支撑。

公开(公告)号：US20060238310A1

公开(公告)日：2006-10-26

申请号：US11298670

申请日：2005-12-12

申请人： Hee Kang ,  Jin Ahn

发明人： Hee Kang ,  Jin Ahn

IPC分类号： H04Q5/22

CPC分类号： G06K19/0723

摘要： A radio frequency identification (RFID) system and a method for correcting a failed cell using the same are provided. The RFID system effectively corrects randomly distributed cell data by using a failed cell correcting circuit in a memory. In the RFID system, a predetermined number of unit cells are separated into one memory group, and the same data are stored in each memory group at a write mode. At a read mode, the cell data of the selected memory group are compared, and the same data are identified as effective data to improve yield of the RFID system.

摘要翻译： 提供射频识别（RFID）系统和使用其的用于校正故障小区的方法。 RFID系统通过使用存储器中的故障单元校正电路来有效地校正随机分布的小区数据。 在RFID系统中，将预定数量的单位单元分成一个存储器组，并且以写入模式将相同的数据存储在每个存储器组中。 在读取模式下，比较所选存储器组的单元数据，将相同的数据识别为有效数据，以提高RFID系统的产量。

公开(公告)号：US20050235088A1

公开(公告)日：2005-10-20

申请号：US11087837

申请日：2005-03-24

申请人： Hee Kang

发明人： Hee Kang

IPC分类号： H04L29/10 ,  G06F13/14 ,  G06F13/40

CPC分类号： G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

摘要： A multi-protocol serial interface system comprises a multi-protocol port pin array, a transport protocol change FPGA, a pull-up change FPGA and a memory. The multi-protocol port pin array comprises a plurality of port pins which interface with an external system for exchanging data with the external system. The transport protocol change FPGA determines roles of port pins of the multi-protocol port pin array depending on a variably changed protocol by selecting one of the plurality of programmed transport protocol circuits in response to code data. The pull-up change FPGA regulates pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA. The memory stores data processed in the transport protocol change FPGA unit and exchanged with the external system.

摘要翻译： 多协议串行接口系统包括多协议端口引脚阵列，传输协议更改FPGA，上拉变换FPGA和存储器。 多协议端口引脚阵列包括与用于与外部系统交换数据的外部系统接口的多个端口引脚。 传输协议更改FPGA根据代码数据选择多个编程的传输协议电路之一，根据可变改变的协议来确定多协议端口引脚阵列的端口引脚的作用。 上拉变化FPGA调节端口引脚的上拉负载，与传输协议变化FPGA中确定的端口引脚的作用相对应。 存储器存储在传输协议中处理的数据改变FPGA单元并与外部系统交换。