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    Nonvolatile memory devices and methods of fabricating the same
    1.
    发明授权
    Nonvolatile memory devices and methods of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US07553725B2

    公开(公告)日：2009-06-30

    申请号：US11488911

    申请日：2006-07-18

    申请人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

    发明人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11524 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

    摘要翻译： 非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。 源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。 非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域 以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。 单元栅极图案和选择线之间的距离小于选择线的宽度。

    Byte-Erasable Nonvolatile Memory Devices
    5.
    发明申请
    Byte-Erasable Nonvolatile Memory Devices 审中-公开
    字节可擦除非易失性存储器件

    公开(公告)号：US20080130367A1

    公开(公告)日：2008-06-05

    申请号：US12027735

    申请日：2008-02-07

    申请人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

    发明人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

    IPC分类号： G11C16/14

    CPC分类号： G11C7/18 ,  G11C16/16 ,  H01L27/115 ,  H01L27/11521

    摘要： A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

    摘要翻译： 非易失性存储器件包括半导体衬底上的第一导电类型的半导体阱区域和在半导体阱区域中延伸的第二导电类型的公共源极扩散区域，并与其形成P-N整流结。 在半导体阱区域中提供一个字节可擦除EEPROM存储器阵列。 该字节可擦除EEPROM存储器阵列被配置为支持其中与公共源扩散区电连接的第一和第二多个EEPROM存储器单元的独立擦除。

    Byte-Erasable Nonvolatile Memory Devices
    6.
    发明申请
    Byte-Erasable Nonvolatile Memory Devices 审中-公开
    字节可擦除非易失性存储器件

    公开(公告)号：US20070091682A1

    公开(公告)日：2007-04-26

    申请号：US11427211

    申请日：2006-06-28

    申请人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

    发明人： Sung-Taeg Kang ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Bo-Young Seo ,  Chang-Min Jeon ,  Eun-Mi Hong

    IPC分类号： G11C16/04

    CPC分类号： G11C16/16 ,  G11C2216/18

    摘要： A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

    摘要翻译： 非易失性存储器件包括半导体衬底上的第一导电类型的半导体阱区域和在半导体阱区域中延伸的第二导电类型的公共源极扩散区域，并与其形成P-N整流结。 在半导体阱区域中提供一个字节可擦除EEPROM存储器阵列。 该字节可擦除EEPROM存储器阵列被配置为支持其中与公共源扩散区电连接的第一和第二多个EEPROM存储器单元的独立擦除。

    Nonvolatile memory devices and methods of fabricating the same
    7.
    发明申请
    Nonvolatile memory devices and methods of fabricating the same 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20070045673A1

    公开(公告)日：2007-03-01

    申请号：US11488911

    申请日：2006-07-18

    申请人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

    发明人： Hee-Seog Jeon ,  Jeong-Uk Han ,  Chang-Hun Lee ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Hyok-Ki Kwon

    IPC分类号： G11C11/34

    CPC分类号： H01L27/11524 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.

    摘要翻译： 非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。 源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。 非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域 以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。 单元栅极图案和选择线之间的距离小于选择线的宽度。

    Semiconductor device and method of fabricating the same
    8.
    发明申请
    Semiconductor device and method of fabricating the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20070102734A1

    公开(公告)日：2007-05-10

    申请号：US11499515

    申请日：2006-08-04

    申请人： Ju-Ri Kim ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Chang-Hun Lee ,  Sung-Chul Park

    发明人： Ju-Ri Kim ,  Jeong-Uk Han ,  Sung-Taeg Kang ,  Chang-Hun Lee ,  Sung-Chul Park

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11568 ,  H01L29/1041 ,  H01L29/792

    摘要： Disclosed is a semiconductor device and method of fabricating the same. The semiconductor device is applicable to various electronic devices such as transistors or memories with transistors. A MOS transistor of the semiconductor device includes a first region and a second region, different in impurity concentration, which are formed in a channel region between source and drain regions. The first region is higher than the second region in impurity concentration. Impurities of the first region are concentrated on a boundary region between an active region and a field isolation film. The first region prevents a punch-through effect in the channel region, while the second region prevents current from decreasing by an increase of impurity during an operation of the transistor. The first region is formed using an additional ion implantation mask, and the second region is formed using an ion implantation mask or formed along with a well.

    摘要翻译： 公开了半导体器件及其制造方法。 半导体器件可应用于各种电子器件，例如具有晶体管的晶体管或存储器。 半导体器件的MOS晶体管包括在源极和漏极区域之间的沟道区域中形成的杂质浓度不同的第一区域和第二区域。 第一区域高于杂质浓度的第二区域。 第一区域的杂质集中在活性区域和场隔离膜之间的边界区域上。 第一区域防止沟道区域中的穿通效应，而第二区域在晶体管的操作期间防止电流由杂质增加而减小。 使用另外的离子注入掩模形成第一区域，并且使用离子注入掩模形成第二区域或与阱一起形成。

    Thin film transistor array panel for liquid crystal display
    9.
    发明授权
    Thin film transistor array panel for liquid crystal display 有权

    公开(公告)号：US08427618B2

    公开(公告)日：2013-04-23

    申请号：US13108782

    申请日：2011-05-16

    申请人： Chang-Hun Lee ,  Eun-Hee Han ,  Hak-Sun Chang

    发明人： Chang-Hun Lee ,  Eun-Hee Han ,  Hak-Sun Chang

    IPC分类号： G02F1/1343

    摘要： Disclosed is a liquid crystal display capable of high quality image and bright display. Gate signal lines are curved at near switching elements of the liquid crystal display. A pixel area is defined by the gate signal lines and their intersecting data signal lines. Pixel electrodes and common electrodes are disposed along a longitudinal direction of a pixel. A pixel signal and a common signal line is connected to the pixel electrode and the common electrode respectively. A storage capacitor may be formed in the middle of a longitudinal direction of the pixel, or where generally a texture may arise during display. One half of the pixel may be symmetrical with the other half with respect to the storage capacitor. A common signal line may be parallel with the data signal line and be disposed nearer to the data signal line than a pixel signal line. The pixel may be disposed symmetrically with respect to the data signal line therebetween. The pixel shape may also be repeated in the direction of the gate signal line.

    Thin film transistor array panel for liquid crystal display and method for manufacturing the same
    10.
    发明授权
    Thin film transistor array panel for liquid crystal display and method for manufacturing the same 有权

    公开(公告)号：US08040446B2

    公开(公告)日：2011-10-18

    申请号：US11697083

    申请日：2007-04-05

    申请人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

    发明人： Chang-Hun Lee ,  Nam-Hung Kim ,  Hak-Sun Chang ,  Jae-Jin Lyu

    IPC分类号： G02F1/1343

    CPC分类号： G02F1/13458 ,  G02F1/13306 ,  G02F1/136213 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255

    摘要： In a method of fabricating a liquid crystal display, an insulating layer for storage capacitors is reduced in thickness to increase the storage capacity while maintaining the aperture ratio in a stable manner. A thin film transistor array panel for the liquid crystal display includes an insulating substrate, and a gate line assembly and a storage capacitor line assembly formed on the insulating substrate. The gate line assembly has gate lines and gate electrodes. A gate insulating layer covers the gate line assembly and the storage capacitor line assembly. A semiconductor pattern is formed on the gate insulating layer. A data line assembly and storage capacitor conductive patterns are formed on the gate insulating layer overlaid with the semiconductor pattern. The data line assembly has data lines, source electrodes and drain electrodes. The storage capacitor conductive patterns are partially overlapped with the storage capacitor line assembly to thereby form first storage capacitors. A passivation layer covers the data line assembly, the storage capacitor conductive patterns and the semiconductor pattern. First and second contact holes are formed at the passivation layer while exposing the drain electrodes and the storage capacitor conductive patterns. Pixel electrodes are formed on the passivation layer while being connected to the drain electrodes and the storage capacitor conductive patterns through the first and the second contact holes. The pixel electrodes form second storage capacitors in association with parts of the storage capacitor line assembly.