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    Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods
    5.
    发明授权
    Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods 有权
    用于产生参考电压和读取存储器单元的方法以及实现该方法的电路配置

    公开(公告)号：US07342819B2

    公开(公告)日：2008-03-11

    申请号：US11368266

    申请日：2006-03-03

    申请人： Corvin Liaw ,  Heinz Hoenigschmid ,  Milena Dimitrova ,  Michael Angerbauer

    发明人： Corvin Liaw ,  Heinz Hoenigschmid ,  Milena Dimitrova ,  Michael Angerbauer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0026 ,  G11C7/12 ,  G11C7/14 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0054

    摘要： A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

    摘要翻译： 用于在电阻半导体存储器中产生参考电压的方法和电路配置包括通过将具有不同电压的两个位线连接在一起来产生参考电压。 用于产生参考电压的方法可以用于读取半导体存储器中的电阻性存储单元阵列的至少一个存储单元的方法和电路配置中。 产生的参考电压和取决于电阻存储器单元的内容的电压被施加到放大器以确定存储器单元的内容。 存储单元的内容取决于参考电压和取决于存储器单元的内容的电压之间的关系。

    Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods
    7.
    发明申请
    Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods 有权
    用于产生参考电压和读取存储器单元的方法以及实现该方法的电路配置

    公开(公告)号：US20070206402A1

    公开(公告)日：2007-09-06

    申请号：US11368266

    申请日：2006-03-03

    申请人： Corvin Liaw ,  Heinz Hoenigschmid ,  Milena Dimitrova ,  Michael Angerbauer

    发明人： Corvin Liaw ,  Heinz Hoenigschmid ,  Milena Dimitrova ,  Michael Angerbauer

    IPC分类号： G11C5/14 ,  G11C11/00

    CPC分类号： G11C13/0026 ,  G11C7/12 ,  G11C7/14 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0054

    摘要： A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

    摘要翻译： 用于在电阻半导体存储器中产生参考电压的方法和电路配置包括通过将具有不同电压的两个位线连接在一起来产生参考电压。 用于产生参考电压的方法可以用于读取半导体存储器中的电阻性存储单元阵列的至少一个存储单元的方法和电路配置。 产生的参考电压和取决于电阻存储器单元的内容的电压被施加到放大器以确定存储器单元的内容。 存储单元的内容取决于参考电压和取决于存储器单元的内容的电压之间的关系。

    Memory circuit having a resistive memory cell and method for operating such a memory circuit
    9.
    发明申请
    Memory circuit having a resistive memory cell and method for operating such a memory circuit 审中-公开
    具有电阻存储单元的存储器电路和用于操作这种存储器电路的方法

    公开(公告)号：US20070195580A1

    公开(公告)日：2007-08-23

    申请号：US11361062

    申请日：2006-02-23

    申请人： Heinz Hoenigschmid ,  Corvin Liaw ,  Milena Dimitrova ,  Michael Angerbauer

    发明人： Heinz Hoenigschmid ,  Corvin Liaw ,  Milena Dimitrova ,  Michael Angerbauer

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C11/16 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79

    摘要： The invention relates to a memory circuit comprising a resistive memory cell having a selection transistor and a resistive memory element connected in series, wherein the resistive memory element is coupled to a plate potential; and a control circuit to control the selection transistor by means of an activation signal a pre-charge circuit coupled with a node between the selection transistor and the resistive memory element and to apply a compensation potential to the node; wherein the control circuit controls the pre-charge circuit so that a compensation potential is applied to the node prior to a level transition of the activation signal.

    摘要翻译： 本发明涉及一种包括具有串联连接的选择晶体管和电阻性存储元件的电阻式存储单元的存储器电路，其中该电阻式存储器元件耦合到一个电位电位; 以及控制电路，通过激活信号控制所述选择晶体管，所述预充电电路与所述选择晶体管和所述电阻性存储器元件之间的节点耦合，并向所述节点施加补偿电位; 其中所述控制电路控制所述预充电电路，使得在所述激活信号的电平转换之前将补偿电位施加到所述节点。

    MEMORY CIRCUIT
    10.
    发明申请
    MEMORY CIRCUIT 审中-公开
    存储器电路

    公开(公告)号：US20080056041A1

    公开(公告)日：2008-03-06

    申请号：US11469746

    申请日：2006-09-01

    申请人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

    发明人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

    IPC分类号： G11C7/02

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/06 ,  G11C2207/005

    摘要： A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

    摘要翻译： 存储电路包括连接到多个存储器单元的多个并行位线，连接到位线的多个读出放大器和多个开关，每个开关连接到相应的一对位线， 所述多个位线用于可切换地使相应的一对位线短路。 相应的位线对的位线连接到两个不同的读出放大器，并且相应的位线对的位线与设置在相应的位线之间的位线之间的另一个位线相邻 一对位线。