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    Memory comprising a memory device and a write unit configured as a probe
    3.
    发明申请
    Memory comprising a memory device and a write unit configured as a probe 审中-公开
    存储器，包括配置为探针的存储器件和写入单元

    公开(公告)号：US20070008863A1

    公开(公告)日：2007-01-11

    申请号：US11176740

    申请日：2005-07-07

    申请人： Corvin Liaw ,  Michael Kund ,  Gerhard Mueller

    发明人： Corvin Liaw ,  Michael Kund ,  Gerhard Mueller

    IPC分类号： G11B9/00

    CPC分类号： G11B9/04 ,  B82Y10/00 ,  G11B9/1427 ,  G11B9/149

    摘要： Embodiments of the present invention provide a method and memory device for storing and reading data. In one embodiment, the probe is positioned proximate to an area of a solid electrolyte layer in which the data is to be stored. A voltage difference is created across the solid electrolyte layer by applying a first voltage to a first side of the solid electrolyte layer via a tip of the probe and applying a second voltage to a second side of the solid electrolyte layer via an electrode layer coupled to the solid electrolyte layer. The voltage difference applied across the solid electrolyte layer causes ions from the electrode layer to be introduced into the solid electrolyte layer, creating a lowered resistance in the solid electrolyte layer. The lowered resistance corresponds to a first logical value stored in the solid electrolyte layer.

    摘要翻译： 本发明的实施例提供一种用于存储和读取数据的方法和存储装置。 在一个实施例中，探针位于其中要存储数据的固体电解质层的区域附近。 通过经由探针的尖端向固体电解质层的第一侧施加第一电压，并通过耦合到固体电解质层的电极层向固体电解质层的第二侧施加第二电压，在固体电解质层上形成电压差 固体电解质层。 施加在固体电解质层两端的电压差使得来自电极层的离子被引入到固体电解质层中，导致固体电解质层中的电阻降低。 降低的电阻对应于存储在固体电解质层中的第一逻辑值。

    Error detection and correction method and apparatus in a magnetoresistive random access memory
    4.
    发明授权
    Error detection and correction method and apparatus in a magnetoresistive random access memory 有权
    磁阻随机存取存储器中的误差检测和校正方法及装置

    公开(公告)号：US06704230B1

    公开(公告)日：2004-03-09

    申请号：US10250201

    申请日：2003-06-12

    申请人： John K. DeBrosse ,  Heinz Hoenigschmid ,  Rainer Leuschner ,  Gerhard Mueller

    发明人： John K. DeBrosse ,  Heinz Hoenigschmid ,  Rainer Leuschner ,  Gerhard Mueller

    IPC分类号： G11C2900

    CPC分类号： G11C7/24 ,  G06F11/106 ,  G11C11/406

    摘要： The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

    摘要翻译： 本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。 根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。 此后，读出数据位和ECC校验位，并检测和校正任何错误。 然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位 并将ECC校验位存储到存储区域。

    Sense amplifier
    5.
    发明授权
    Sense amplifier 有权
    感应放大器

    公开(公告)号：US06420908B2

    公开(公告)日：2002-07-16

    申请号：US09225665

    申请日：1999-01-05

    申请人： Gerhard Mueller ,  Heinz Hoenigschmid

    发明人： Gerhard Mueller ,  Heinz Hoenigschmid

    IPC分类号： G01R1900

    CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C11/4091

    摘要： Providing an active signal that increases the gate overdrive voltage of the driver of a sense amplifier enables the use of smaller drivers. This facilitates more efficient layouts and/or smaller sense amplifiers, thereby reducing the chip size.

    摘要翻译： 提供增加读出放大器的驱动器的栅极过驱动电压的有源信号使得能够使用较小的驱动器。 这有助于更有效的布局和/或更小的感测放大器，从而减小芯片尺寸。

    Space-efficient semiconductor memory having hierarchical column select line architecture
    6.
    发明授权
    Space-efficient semiconductor memory having hierarchical column select line architecture 失效
    节省空间的半导体存储器具有分层列选择线架构

    公开(公告)号：US5923605A

    公开(公告)日：1999-07-13

    申请号：US940861

    申请日：1997-09-29

    申请人： Gerhard Mueller ,  Heinz Hoenigschmid

    发明人： Gerhard Mueller ,  Heinz Hoenigschmid

    IPC分类号： G11C11/41 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C8/00

    CPC分类号： G11C8/10 ,  G11C11/4087

    摘要： Disclosed is a multiple bank semiconductor memory (40) (e.g., DRAM) capable of overlapping write/read operation to/from memory cells of different banks (MAa, MAb), and having a space efficient layout. Chip size is kept small by employing a single column decoder (44) for different banks, and a hierarchical column select line architecture, with bit line switches (59, 61, 63, 65) of different columns having a shared active area such as a common source region. In an illustrative embodiment, global column select lines (GCSL.sub.1 -GCSL.sub.(N/K)) selectively activate global bit line switches (67, 68) which are coupled to bank-specific data lines (LDQ, LDQ). Several bank bit line switches (59-66) are coupled to each global bit line switch, with two or more bank bit line switches of different columns having a shared diffusion region to realize a compact layout.

    摘要翻译： 公开了一种能够将写/读操作与不同存储体（MAa，MAb）的存储单元重叠并且具有空间有效布局的多存储体半导体存储器（40）（例如DRAM）。 通过对不同的组使用单列解码器（44）和具有不同列的位线开关（59,61,63,65）的分层列选择线架构来保持较小的芯片尺寸，该列具有共享的有效区域，例如 公共源区。 在说明性实施例中，全局列选择线（GCSL1-GCSL（N / K））选择性地激活耦合到组专用数据线（LDQ，+ E，ovs LDQ + EE）的全局位线开关（67,68） 。 几个银行位线开关（59-66）耦合到每个全局位线开关，具有不同列的两个或多个库位线开关具有共享扩散区域以实现紧凑的布局。

    High density semiconductor memory having diagonal bit lines and dual word lines
    7.
    发明授权
    High density semiconductor memory having diagonal bit lines and dual word lines 失效
    具有对角位线和双字线的高密度半导体存储器

    公开(公告)号：US5864496A

    公开(公告)日：1999-01-26

    申请号：US939455

    申请日：1997-09-29

    申请人： Gerhard Mueller ,  Toshiaki Kirihata ,  Heinz Hoenigschmid

    发明人： Gerhard Mueller ,  Toshiaki Kirihata ,  Heinz Hoenigschmid

    IPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  G11C5/08

    CPC分类号： H01L27/10891 ,  G11C11/4097 ,  G11C7/18 ,  H01L27/10861

    摘要： The semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP.sub.1 -BLP.sub.N) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL.sub.1 -WL.sub.M), where each dual word line includes a master word line (MWL.sub.i) at a first layer and a plurality of local word lines (LWL.sub.1 -LWL.sub.X) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.

    摘要翻译： 半导体存储器包括以行和列排列的存储器单元的存储单元阵列（10）和以沿存储单元阵列改变水平方向的图案布置的多个对角位线（BLP1-BLPN），以便于访问所述 记忆细胞 位线布置成与多条双字线（WL1-WLM）非正交，其中每个双字线包括第一层的主字线（MWLi）和多个本地字线（LWL1-LWLX） 在第二层。 本地字线经由多个间隔的电连接（29）连接到公共行的主字线，例如“缝合”结构中的电触点，并且每个本地字线连接到多个存储单元（MC ）。 电连接沿着与位线的存储单元阵列基本上相同的图案运行。

    Optical module for simultaneously focusing on two fields of view
    8.
    发明授权
    Optical module for simultaneously focusing on two fields of view 有权
    用于同时聚焦于两个视野的光学模块

    公开(公告)号：US09040915B2

    公开(公告)日：2015-05-26

    申请号：US13382405

    申请日：2010-06-22

    申请人： Konrad Rothenhaeusler ,  Gerhard Mueller ,  Lutz Kuehnke

    发明人： Konrad Rothenhaeusler ,  Gerhard Mueller ,  Lutz Kuehnke

    IPC分类号： G01J1/44 ,  G01J5/20 ,  G01J1/06 ,  H04N5/225 ,  B60S1/08

    CPC分类号： H04N5/2254 ,  B60S1/0844 ,  G06K9/00791

    摘要： The invention relates to an optical module, comprising a semiconductor element having a surface that is sensitive to electromagnetic radiation and an objective for projecting electromagnetic radiation onto the sensitive surface of the semiconductor element (image sensor or camera chip, in particular CCD or CMOS). The objective preferably comprises at least one lens and one lens retainer.In the optical module, an optical element having two sub-areas is arranged either in the space between the objective and the sensitive surface of the semiconductor element or between individual lenses of the objective in the entire cross-section of the beam path. All electromagnetic radiation that reaches the sensitive surface of the semiconductor element passes through the optical element.A first distance range (e.g. near range) is imaged in a first area of the sensitive surface of the semiconductor element in a focused manner by a first sub-area of the optical element, and a second distance range (e.g. far range) is imaged in a second area of the sensitive surface of the semiconductor element by a second sub-area.

    摘要翻译： 本发明涉及一种光学模块，包括具有对电磁辐射敏感的表面的半导体元件和用于将电磁辐射投射到半导体元件（图像传感器或照相机芯片，特别是CCD或CMOS）的敏感表面上的物镜。 该目的优选地包括至少一个透镜和一个透镜保持器。 在光学模块中，具有两个子区域的光学元件被布置在物镜和半导体元件的敏感表面之间的空间中，或者布置在光束路径的整个横截面中的物镜的各个透镜之间。 到达半导体元件的敏感表面的所有电磁辐射通过光学元件。 将第一距离范围（例如近距离）以聚焦方式由该光学元件的第一子区域成像在半导体元件的敏感表面的第一区域中，并且第二距离范围（例如，远距离）被成像 在第二子区域的半导体元件的敏感表面的第二区域中。