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    MEMORY CIRCUIT
    1.
    发明申请
    MEMORY CIRCUIT 审中-公开
    存储器电路

    公开(公告)号：US20080056041A1

    公开(公告)日：2008-03-06

    申请号：US11469746

    申请日：2006-09-01

    申请人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

    发明人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

    IPC分类号： G11C7/02

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/06 ,  G11C2207/005

    摘要： A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

    摘要翻译： 存储电路包括连接到多个存储器单元的多个并行位线，连接到位线的多个读出放大器和多个开关，每个开关连接到相应的一对位线， 所述多个位线用于可切换地使相应的一对位线短路。 相应的位线对的位线连接到两个不同的读出放大器，并且相应的位线对的位线与设置在相应的位线之间的位线之间的另一个位线相邻 一对位线。

    Memory device and method of improving the reliability of a memory device
    2.
    发明申请
    Memory device and method of improving the reliability of a memory device 审中-公开
    存储器件和提高存储器件可靠性的方法

    公开(公告)号：US20080043544A1

    公开(公告)日：2008-02-21

    申请号：US11507381

    申请日：2006-08-21

    申请人： Corvin Liaw ,  Milena Dimitrova ,  Michael Markert ,  Stefan Dietrich

    发明人： Corvin Liaw ,  Milena Dimitrova ,  Michael Markert ,  Stefan Dietrich

    IPC分类号： G11C7/00

    CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C7/1078 ,  G11C7/1096 ,  G11C2207/2227

    摘要： A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being electrically connected to the bitlines and amplifying electrical signals carried in the bitlines, the amplifier circuits being activated and deactivated by means of amplifier circuit control nodes, and at least one potential supplying unit, by means of which potentials can be supplied to the amplifier circuits such that, in the deactivated state of the amplifier circuits, a decrease or a prevention of leakage currents through the amplifier circuits is caused.

    摘要翻译： 存储器件包括存储单元阵列，其包括多个存储器单元，位线电连接到存储单元阵列的存储单元，放大器电路电连接到位线并放大位线中承载的电信号，放大器电路为 通过放大器电路控制节点激活和去激活，以及至少一个电位供应单元，通过该电势供应单元可以将电位提供给放大器电路，使得在放大器电路的去激活状态下，减小或防止泄漏 引起通过放大器电路的电流。

    INTEGRATED CIRCUIT HAVING A RESISTIVELY SWITCHING MEMORY AND METHOD
    3.
    发明申请
    INTEGRATED CIRCUIT HAVING A RESISTIVELY SWITCHING MEMORY AND METHOD 失效
    具有电阻开关存储器和方法的集成电路

    公开(公告)号：US20080239788A1

    公开(公告)日：2008-10-02

    申请号：US11693391

    申请日：2007-03-29

    申请人： Michael Markert ,  Milena Dimitrova ,  Heinz Hoenigschmid

    发明人： Michael Markert ,  Milena Dimitrova ,  Heinz Hoenigschmid

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/009

    摘要： An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage.

    摘要翻译： 公开了一种具有电阻或电阻切换存储单元的集成电路，以及用于操作电阻切换存储单元的方法。 一个实施例适于通过施加第一阈值电压并且通过施加第二阈值电压处于高电阻状态而被置于低电阻状态，其中通过施加电压来执行从存储器单元读出数据内容 在第一或第二阈值电压或较高电压的范围内到存储单元。

    Integrated circuit having a resistively switching memory and method
    4.
    发明授权
    Integrated circuit having a resistively switching memory and method 失效
    具有电阻切换存储器和方法的集成电路

    公开(公告)号：US07656697B2

    公开(公告)日：2010-02-02

    申请号：US11693391

    申请日：2007-03-29

    申请人： Michael Markert ,  Milena Dimitrova ,  Heinz Hoenigschmid

    发明人： Michael Markert ,  Milena Dimitrova ,  Heinz Hoenigschmid

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0011 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/009

    摘要： An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage.

    摘要翻译： 公开了一种具有电阻或电阻切换存储单元的集成电路，以及用于操作电阻切换存储单元的方法。 一个实施例适于通过施加第一阈值电压并且通过施加第二阈值电压处于高电阻状态而被置于低电阻状态，其中通过施加电压来执行从存储器单元读出数据内容 在第一或第二阈值电压或较高电压的范围内到存储单元。

    INTEGRATED CIRCUIT HAVING A MEMORY ARRAY
    6.
    发明申请
    INTEGRATED CIRCUIT HAVING A MEMORY ARRAY 审中-公开
    具有存储阵列的集成电路

    公开(公告)号：US20080205179A1

    公开(公告)日：2008-08-28

    申请号：US11680305

    申请日：2007-02-28

    申请人： Michael Markert ,  Michael Angerbauer ,  Corvin Liaw

    发明人： Michael Markert ,  Michael Angerbauer ,  Corvin Liaw

    IPC分类号： G11C7/12

    CPC分类号： G11C13/0011 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009

    摘要： An integrated circuit having a memory array and a method for reducing sneak current in a memory array is disclosed.One embodiment provides a memory array including a plurality of storage devices arranged as a plurality of rows and a plurality of columns. A first voltage is applied to a particular word line to select a column of storage devices. A second voltage is applied to a particular bit line of the plurality of bit lines to select a row of storage devices, and the second voltage is applied to each of further lines except for a further line being connected to the storage devices of the selected column.

    摘要翻译： 公开了一种具有存储器阵列的集成电路和用于减少存储器阵列中的潜行电流的方法。 一个实施例提供一种存储器阵列，其包括被布置为多行和多列的多个存储装置。 将第一电压施加到特定字线以选择一列存储设备。 第二电压被施加到多个位线的特定位线以选择一行存储装置，并且第二电压被施加到每个其它线，除了连接到所选列的存储装置的另外的线 。

    FB DRAM memory with state memory
    7.
    发明授权
    FB DRAM memory with state memory 有权
    FB DRAM内存带状态存储器

    公开(公告)号：US07848134B2

    公开(公告)日：2010-12-07

    申请号：US12178407

    申请日：2008-07-23

    申请人： Milena Ivanov ,  Heinz Hoenigschmid ,  Stefan Dietrich ,  Michael Markert

    发明人： Milena Ivanov ,  Heinz Hoenigschmid ,  Stefan Dietrich ,  Michael Markert

    IPC分类号： G11C11/24

    CPC分类号： G11C11/4091 ,  G11C11/404 ,  G11C2211/4016

    摘要： A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.

    摘要翻译： 公开了具有耦合到第一FB DRAM单元和第二FB DRAM单元的字线的具有多个FB DRAM单元的存储器芯片。 存储器芯片还具有耦合到第一FB DRAM单元的第一位线和耦合到第一位线的第一状态存储器电路。 存储器芯片还包括耦合到第二FB DRAM单元的第二位线和耦合到第二位线的第二状态存储器电路。 存储器芯片还包括读出放大器，其可耦合到第一FB DRAM单元，第二FB DRAM单元，第一状态存储器电路或第二状态存储器电路。

    Integrated memory, and a method of operating an integrated memory
    9.
    发明授权
    Integrated memory, and a method of operating an integrated memory 失效
    集成存储器以及操作集成存储器的方法

    公开(公告)号：US06882554B2

    公开(公告)日：2005-04-19

    申请号：US10287501

    申请日：2002-11-04

    申请人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    发明人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    IPC分类号： G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06

    CPC分类号： G11C7/067 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/105

    摘要： An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

    摘要翻译： 集成存储器具有用于激活读/写放大器的行线，列线和列选择线。 在每种情况下，一组预定数量的存储单元属于行和列地址。 此外，存储器具有对应于预定数量的多个连接焊盘。 一组存储器单元中的每个存储器单元与一个连接焊盘相关联。 设计用于控制存储器访问的控制电路，并且可以操作该控制电路，使得通过列地址激活至少两个不同的列选择线。 对于两个或更多列地址，其中一列列选择行被激活。 因此，可以减小存储芯片上的延迟时间和线路长度。