公开(公告)号：US07606057B2

公开(公告)日：2009-10-20

申请号：US11443443

申请日：2006-05-31

Applicant: Karl Lin Wang ,  Hemangi Umakant Gajjewar

Inventor： Karl Lin Wang ,  Hemangi Umakant Gajjewar

IPC: G11C11/00

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/18 ,  H01L27/1104

Abstract: A memory cell includes polysilicon gates 2 running in a first direction. A sequence of layers metal lines includes a layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed by data lines 6 running in that second direction and then word lines 8 running in the first direction. The data lines 6 are precharged to a value which is held whilst the bit lines 4 are being used to sense data values stored within a memory cell.

Abstract translation: 存储单元包括在第一方向上运行的多晶硅栅极2。 一层层金属线包括沿与第一方向大致正交的第二方向运行的位线4，随后是在该第二方向上运行的数据线6，然后在第一方向上运行的字线8。 数据线6被预充电到在位线4被用于感测存储在存储器单元中的数据值时被保持的值。

公开(公告)号：US08004913B2

公开(公告)日：2011-08-23

申请号：US12801066

申请日：2010-05-20

Applicant: Hemangi Umakant Gajjewar ,  Karl Lin Wang

Inventor： Hemangi Umakant Gajjewar ,  Karl Lin Wang

IPC: G11C7/00

CPC classification number: G11C29/848 ,  G11C29/808

Abstract: An integrated circuit memory includes multiple memory banks grouped into repair groups Group0, Group1. One memory has redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Abstract translation: 集成电路存储器包括分组为修复组Group0，Group1的多个存储体。 一个存储器具有冗余行，其可以用于替代在相关公共修复组内的任何存储体中找到的缺陷行。 存储器单元的冗余列可以通过复用电路代替缺陷列。 该多路复用电路将选择的位线移位以形成位组的一部分，以访问给定数据位的量小于该复用电路所支持的多路复用宽度，从而减少需要提供的冗余列的数量。

公开(公告)号：US20080259701A1

公开(公告)日：2008-10-23

申请号：US11785583

申请日：2007-04-18

Applicant: Hemangi Umakant Gajjewar ,  Karl Lin Wang

Inventor： Hemangi Umakant Gajjewar ,  Karl Lin Wang

IPC: G11C29/04

CPC classification number: G11C29/848 ,  G11C29/808

Abstract: An integrated circuit memory 2 is described having multiple memory banks 4, 6, 8, 10, 12, 14, 16, 18 which are grouped into repair groups Group0, Group1. One of the memory banks 4, 18 is provided with redundant rows 20, 22 which can be used to substitute for a defective row 30, 32, 34 found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells 60, 62 are also provided and these may be substituted for defective columns 66, 68 by multiplexing circuitry 56, 58. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry 56, 58 thereby reducing the number of redundant columns which need be provided.

Abstract translation: 描述了具有多个存储体组4,6,8,10,12,14,16,18的集成电路存储器2，它们分组成维修组组0，组1。 存储器组4,18中的一个设置有冗余行20,22，其可用于替代在相关公共修复组内的任何存储体中发现的有缺陷的行30,32,34。 还提供了存储单元60,62的冗余列，并且它们可以通过复用电路56,58来代替缺陷列66,68。 该多路复用电路将选择的位线移位以形成位组的一部分，以访问给定数据位小于多路复用电路56,58支持的多路复用宽度的量，从而减少需要的冗余列数 提供。

公开(公告)号：US07924638B2

公开(公告)日：2011-04-12

申请号：US11785583

申请日：2007-04-18

Applicant: Hemangi Umakant Gajjewar ,  Karl Lin Wang

Inventor： Hemangi Umakant Gajjewar ,  Karl Lin Wang

IPC: G11C7/00

CPC classification number: G11C29/848 ,  G11C29/808

Abstract: An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Abstract translation: 描述了具有多个存储体的集成电路存储器，其被分组为维修组Group0，Group1。 其中一个存储器组被提供有冗余的行，其可用于替代在相关公共修复组内的任何存储体中找到的有缺陷的行。 还提供了存储器单元的冗余列，并且这些列可以通过复用电路代替缺陷列。 该多路复用电路移位被选择以形成位组的一部分的位线，以访问给定数据位小于该多路复用电路支持的多路复用宽度的量，从而减少需要提供的冗余列的数量。

公开(公告)号：US07324368B2

公开(公告)日：2008-01-29

申请号：US11392961

申请日：2006-03-30

Applicant: Karl Lin Wang ,  Hemangi Umakant Gajjewar

Inventor： Karl Lin Wang ,  Hemangi Umakant Gajjewar

IPC: G11C11/00

CPC classification number: G11C11/419

Abstract: An integrated circuit memory includes memory cells 2 is connected to a power supply Vdd via a power supply control circuit 4. The power supply control circuit includes a first gate 26 and a second gate 28. The first gate 26 is switched by a write assist circuit so as to be non-conductive when writing to the memory cell 2. The second gate 28 is conductive both when writing to the memory cell 2 and when not writing to the memory cell 2. Accordingly, when a write operation is made a relatively high resistance path is formed through the power supply control circuit 4 compared to when writing is not being performed. This increase in the resistance through the power supply control circuit 4 during write operations induces a dip in the virtual supply voltage provided at the supply output of the power supply control circuit 4 in a manner which assist writes to be made. If individual memory cells 2 tend to resist changes in their state more strongly, then they will tend to draw more current which will in turn result in a larger virtual supply voltage dip which will assist more strongly in encouraging those memory cells 2 to change state.

Abstract translation: 集成电路存储器包括存储单元2经由电源控制电路4连接到电源Vdd。 电源控制电路包括第一门26和第二门28。 第一门26由写辅助电路切换，以便在写入存储单元2时不导通。 第二栅极28在写入存储单元2时以及当不写入存储单元2时都是导通的。 因此，当写入操作时，与不进行写入时相比，通过电源控制电路4形成相对较高的电阻路径。 在写入操作期间通过电源控制电路4的电阻的这种增加引起以辅助写入的方式在电源控制电路4的电源输出处提供的虚拟电源电压的下降。 如果单独的存储单元2倾向于更强烈地抵抗其状态的变化，则它们将倾向于吸收更多的电流，这又将导致更大的虚拟电源电压下降，这将更有助于鼓励这些存储器单元2改变状态。

公开(公告)号：US20070279959A1

公开(公告)日：2007-12-06

申请号：US11443443

申请日：2006-05-31

Applicant: Karl Lin Wang ,  Hemangi Umakant Gajjewar

Inventor： Karl Lin Wang ,  Hemangi Umakant Gajjewar

IPC: G11C5/06

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/18 ,  H01L27/1104

Abstract: A memory cell is provided having polysilicon gates 2 running in a first direction. A sequence of layers metal lines are provided including layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed data lines 6 running in that second direction and then word lines 8 running in the first direction. The data lines 6 are precharged to a value which is held whilst the bit lines 4 are being used to sense data values stored within a memory cell.

Abstract translation: 提供具有在第一方向上运行的多晶硅栅极2的存储单元。 提供了一系列层金属线，包括沿与第一方向大致正交的第二方向上运行的位线层4，跟随在第二方向上运行的数据线6，然后沿着第一方向运行的字线8。 数据线6被预充电到在位线4被用于感测存储在存储器单元中的数据值时被保持的值。

公开(公告)号：US20100232241A1

公开(公告)日：2010-09-16

申请号：US12801066

申请日：2010-05-20

Applicant: Hemangi Umakant Gajjewar ,  Karl Lin Wang

Inventor： Hemangi Umakant Gajjewar ,  Karl Lin Wang

IPC: G11C29/04

CPC classification number: G11C29/848 ,  G11C29/808

Abstract: An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Abstract translation: 描述了具有多个存储体的集成电路存储器，其被分组为维修组Group0，Group1。 其中一个存储器组被提供有冗余的行，其可用于替代在相关公共修复组内的任何存储体中找到的有缺陷的行。 还提供了存储器单元的冗余列，并且这些列可以通过复用电路代替缺陷列。 该多路复用电路移位被选择以形成位组的一部分的位线，以访问给定数据位小于该多路复用电路支持的多路复用宽度的量，从而减少需要提供的冗余列的数量。

公开(公告)号：US07920411B2

公开(公告)日：2011-04-05

申请号：US12379616

申请日：2009-02-25

Applicant: Ingming Chang ,  Karl Lin Wang

Inventor： Ingming Chang ,  Karl Lin Wang

IPC: G11C11/40

CPC classification number: G11C11/412 ,  G11C17/12 ,  G11C17/146

Abstract: A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled inverters. It is converted to a read only memory cell by severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value.

Abstract translation: 公开了一种将静态随机存取存储器单元转换为仅读存储器单元和如此转换的单元的方法。 要转换的单元包括由较高和较低电压电源线供电的数据保持部分和布置为两个交叉耦合的反相器的四个晶体管。 通过切断所述两个逆变器中的第一个中的至少一个所述晶体管与所述电压供给线中的一个之间的连接，使得当所述第一反相器输出预定值时被转换为只读存储器单元。

公开(公告)号：US20100214824A1

公开(公告)日：2010-08-26

申请号：US12379616

申请日：2009-02-25

Applicant: Ingming Chang ,  Karl Lin Wang

Inventor： Ingming Chang ,  Karl Lin Wang

IPC: G11C11/00 ,  G11C5/14 ,  G11C7/00

CPC classification number: G11C11/412 ,  G11C17/12 ,  G11C17/146

Abstract: A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled inverters. It is converted to a read only memory cell by severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value.

Abstract translation: 公开了一种将静态随机存取存储器单元转换为仅读存储器单元和如此转换的单元的方法。 要转换的单元包括由较高和较低电压电源线供电的数据保持部分和布置为两个交叉耦合的反相器的四个晶体管。 通过切断所述两个逆变器中的第一个中的至少一个所述晶体管与所述电压供给线中的一个之间的连接，使得当所述第一反相器输出预定值时被转换为只读存储器单元。

公开(公告)号：US07289373B1

公开(公告)日：2007-10-30

申请号：US11447292

申请日：2006-06-06

Applicant: Moon-Hae Son ,  Karl Lin Wang

Inventor： Moon-Hae Son ,  Karl Lin Wang

IPC: G11C7/00

CPC classification number: G11C7/14 ,  G11C7/067 ,  G11C7/08 ,  G11C7/12

Abstract: A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected to its inputs, and is arranged to connect one of those inputs to its output dependent on a multiplexer control signal. Decoder logic is responsive to an address to produce the multiplexer control signal and to select one of the word lines, as a result of which a particular memory cell in the memory array identified by the address has its associated bit line connected to the output of a multiplexer logic. Sense amp logic is coupled to the output of the multiplexer logic and has a precharge node used during a sensing operation to detect a stored data state of the particular memory cell. Control logic initiates the sensing operation and causes the precharge node of the sense amp and at least the bit line associated with the particular memory cell to be precharged in a precharge operation prior to the sensing operation. Further, isolation logic is provided between the output of the multiplexer logic and the precharge node of the sense amp logic to isolate the precharge node from the capacitance of the output of the multiplexer logic during the sensing operation.

Abstract translation: 提供了一种存储器件，其包括由多个存储器单元组成的存储器阵列。 这些存储单元通过多个字线和多个位线进行访问。 提供了多路复用器逻辑，其具有连接到其输入的多个位线，并且被布置为根据多路复用器控制信号将那些输入中的一个连接到其输出。 解码器逻辑响应于地址以产生多路复用器控制信号并选择字线之一，结果由地址识别的存储器阵列中的特定存储单元具有与其相关联的位线连接 多路复用逻辑 感测放大器逻辑耦合到多路复用器逻辑的输出，并且具有在感测操作期间使用的预充电节点，以检测特定存储器单元的存储的数据状态。 控制逻辑启动感测操作，并且使感测放大器的预充电节点和至少与特定存储器单元相关联的位线在感测操作之前的预充电操作中被预充电。 此外，在多路复用器逻辑的输出和读出放大器逻辑的预充电节点之间提供隔离逻辑，以在感测操作期间隔离预充电节点与多路复用器逻辑的输出的电容。