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公开(公告)号：US08527822B2
公开(公告)日：2013-09-03
申请号：US12581651
申请日：2009-10-19
申请人： Henk Boezen , Leon Van de Logt , Liquan Fang
发明人： Henk Boezen , Leon Van de Logt , Liquan Fang
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318572 , G01R31/318536
摘要： An electronic circuit having a boundary scan test circuit receives, though one pin, an embedded clock encoded test signal having an encoded bit stream having occurrences of a first header followed by at least one encoded boundary scan mode bit and an encoded second header followed by at least one boundary scan test input bit. The bit stream and the clock are extracted and occurrences of the first header and second header are detected. Based on the detected occurrences the boundary scan mode bits and boundary scan input bits are identified and distributed to the electronic circuit, along with the extracted clock, and boundary scan test is performed.
摘要翻译： 具有边界扫描测试电路的电子电路通过一个引脚接收具有编码比特流的嵌入式时钟编码测试信号，所述编码比特流具有出现的第一标题，随后是至少一个编码边界扫描模式位和编码后的第二标题， 至少一个边界扫描测试输入位。 提取比特流和时钟，并检测出第一首标和第二首标的出现。 基于检测到的事件，边界扫描模式位和边界扫描输入位与提取的时钟一起识别并分配给电子电路，并进行边界扫描测试。
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公开(公告)号：US20110093751A1
公开(公告)日：2011-04-21
申请号：US12581651
申请日：2009-10-19
申请人： Henk Boezen , Leon Van de Logt , Liquan Fang
发明人： Henk Boezen , Leon Van de Logt , Liquan Fang
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318572 , G01R31/318536
摘要： An electronic circuit having a boundary scan test circuit receives, though one pin, an embedded clock encoded test signal having an encoded bit stream having occurrences of a first header followed by at least one encoded boundary scan mode bit and an encoded second header followed by at least one boundary scan test input bit. The bit stream and the clock are extracted and occurrences of the first header and second header are detected. Based on the detected occurrences the boundary scan mode bits and boundary scan input bits are identified and distributed to the electronic circuit, along with the extracted clock, and boundary scan test is performed.
摘要翻译： 具有边界扫描测试电路的电子电路通过一个引脚接收具有编码比特流的嵌入式时钟编码测试信号，所述编码比特流具有出现的第一标题，随后是至少一个编码边界扫描模式位和编码后的第二标题， 至少一个边界扫描测试输入位。 提取比特流和时钟，并检测出第一首标和第二首标的出现。 基于检测到的事件，边界扫描模式位和边界扫描输入位与提取的时钟一起识别并分配给电子电路，并进行边界扫描测试。
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公开(公告)号：US20110260782A1
公开(公告)日：2011-10-27
申请号：US13144337
申请日：2010-01-13
IPC分类号： G05F1/565
CPC分类号： G05F1/565
摘要： A power supply regulator circuit uses a feedback loop to control current through a first output transistor from a power supply input to a regulated power supply output. The first output transistor is included in an integrated circuit. In order to avoid heating of the integrated circuit in excess of an acceptable level due to permanent supply of a high current through the first transistor, current through a second output transistor in parallel with the first transistor, but outside the integrated circuit is raised when it is detected that the current through the first output transistor exceeds a threshold level. The second output transistor outside the integrated circuit serves to take over supply of a part of the power supply current from first output transistor inside integrated circuit, when long term supply of that part from first output transistor would lead to undesirable heating of the integrated circuit. During a limited time interval a first transistor current above the threshold level is acceptable. During this time interval the current through the second output transistor is raised slowly in order to avoid unpredictable stability problems and the generation of excessive power supply noise.
摘要翻译： 电源调节器电路使用反馈回路来控制从电源输入到稳压电源输出的第一输出晶体管的电流。 第一输出晶体管包含在集成电路中。 为了避免由于通过第一晶体管的高电流的永久供应而使集成电路的加热超过可接受的电平，通过与第一晶体管并联的第二输出晶体管，但是当集成电路的外部集成 检测到通过第一输出晶体管的电流超过阈值电平。 集成电路外部的第二输出晶体管用于从集成电路内部的第一输出晶体管接收一部分电源电流，当来自第一输出晶体管的该部分的长期供应将导致集成电路的不期望的加热时。 在有限的时间间隔内，高于阈值电平的第一晶体管电流是可接受的。 在该时间间隔期间，缓慢升高通过第二输出晶体管的电流，以避免不可预测的稳定性问题和产生过大的电源噪声。
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公开(公告)号：US08818265B2
公开(公告)日：2014-08-26
申请号：US13454815
申请日：2012-04-24
申请人： Peter Gerard Steeneken , Maarten Jacobus Swanenberg , Henk Boezen , Gerhard Koops , Frans Bontekoe , Reinout Woltjer
发明人： Peter Gerard Steeneken , Maarten Jacobus Swanenberg , Henk Boezen , Gerhard Koops , Frans Bontekoe , Reinout Woltjer
摘要： One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.
摘要翻译： 一个或多个实施例提供用于使用电容耦合在不同电压域中工作的电路之间的信号的隔离和通信的电路。 与先前的平行板实现相比，这些实施例利用具有增加的击穿电压的电容结构。 电容隔离由平行板电容结构提供，每个电容结构被实现为具有不同水平尺寸的平行板。 由于水平尺寸的差异，电场最强的平行板的边缘与平行板重叠的区域横向偏移。 结果，平行板之间的击穿电压增加。
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公开(公告)号：US08324935B2
公开(公告)日：2012-12-04
申请号：US13122911
申请日：2009-10-08
申请人： Henk Boezen
发明人： Henk Boezen
IPC分类号： H03K19/0175 , H03B1/00
CPC分类号： H04L25/028
摘要： A bus driver circuit for driving a bus voltage is provided. The bus driver circuit comprises: a bus line output (CANL) the bus voltage of which is driven by the bus driver circuit; a first transistor (M1) having a gate, the voltage at the gate of the first transistor (M1) determining the bus voltage at the bus line output (CANL); a first capacitor (C1) connected to the gate of the first transistor (M1) for driving the voltage at the gate of the first transistor (M1); a first switch (S1) connecting/disconnecting the first capacitor (C1) to a first voltage source (Vgm) via a first RC network comprising at least one resistor and at least one capacitor; and a second switch (S2) connecting/disconnecting the first capacitor (C1) to a predetermined fixed potential (GND 2) for discharging the first capacitor (C1) via a second RC network comprising at least one resistor and at least one capacitor. The first switch (S1) and the second switch (S2) are complementarily driven by a signal (TxD) on a data line.
摘要翻译： 提供用于驱动总线电压的总线驱动电路。 总线驱动电路包括：母线电压由总线驱动电路驱动的总线输出（CANL）; 具有栅极的第一晶体管（M1），第一晶体管（M1）的栅极处的电压确定总线输出端（CANL）处的总线电压; 连接到第一晶体管（M1）的栅极的第一电容器（C1），用于驱动第一晶体管（M1）的栅极处的电压; 经由包括至少一个电阻器和至少一个电容器的第一RC网络将第一电容器（C1）连接/断开到第一电压源（Vgm）的第一开关（S1） 以及通过包括至少一个电阻器和至少一个电容器的第二RC网络将第一电容器（C1）连接/断开到预定固定电位（GND2）以用于对第一电容器（C1）进行放电的第二开关（S2）。 第一开关（S1）和第二开关（S2）由数据线上的信号（TxD）互补地驱动。
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公开(公告)号：US09192014B2
公开(公告)日：2015-11-17
申请号：US13275634
申请日：2011-10-18
CPC分类号： H05B33/0887 , H05B33/0815 , H05B33/0851 , Y02B20/341
摘要： According to an example embodiment of the present disclosure, a method is provided for controlling a light-emitting-diode (LED) circuit. The method includes receiving a direct current to direct current (DC-to-DC) control signal at a DC-to-DC converter. A DC voltage is generated from an input DC voltage source. The DC voltage has a voltage level that is set according to the DC-to-DC control signal. The DC voltage is provided to an LED circuit output. The DC voltage level from the DC-to-DC converter is determined. The DC-to-DC converter control signal is generated in response to the determined DC voltage level. The LED circuit is determined to have a short circuit based upon the determined DC voltage. In response to determining that the LED circuit has a short circuit, the DC-to-DC converter is disabled from providing the DC voltage to the output for powering an LED circuit.
摘要翻译： 根据本公开的示例性实施例，提供了一种用于控制发光二极管（LED）电路的方法。 该方法包括在DC-DC转换器处接收直流电流到直流（DC-DC）控制信号。 从输入直流电压源产生直流电压。 DC电压具有根据DC-DC控制信号设定的电压电平。 将直流电压提供给LED电路输出。 确定DC-DC转换器的直流电压电平。 响应于确定的DC电压电平而产生DC-DC转换器控制信号。 根据确定的直流电压，确定LED电路具有短路。 响应于确定LED电路具有短路，DC-DC转换器禁止向输出端提供DC电压以为LED电路供电。
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公开(公告)号：US08305099B2
公开(公告)日：2012-11-06
申请号：US12873236
申请日：2010-08-31
申请人： Henk Boezen
发明人： Henk Boezen
IPC分类号： G01R31/3187
CPC分类号： H04L1/24
摘要： A full duplex, high speed test interface comprises a tester side circuit and a device under test side circuit, each comprising balancing circuits. The balancing circuit of the test side circuit is configured to cancel its own transmitted data at the test side circuit such that the transmitted data does not influence any other signal generated at the test side circuit. Similarly, the balancing circuit of the device under test side circuit is configured to cancel its own transmitted data at the device under test side circuit such that the transmitted data does not influence any other signal generated at the device under test side circuit.
摘要翻译： 全双工，高速测试接口包括测试器侧电路和被测器件侧电路，每个均包括平衡电路。 测试侧电路的平衡电路被配置为在测试侧电路上取消其自身的发送数据，使得所发送的数据不影响在测试侧电路产生的任何其它信号。 类似地，被测器件侧电路的平衡电路被配置为在被测器件侧电路上取消其自己的发送数据，使得所发送的数据不影响在被测器件侧电路产生的任何其它信号。
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公开(公告)号：US20110199131A1
公开(公告)日：2011-08-18
申请号：US13122911
申请日：2009-10-08
申请人： Henk Boezen
发明人： Henk Boezen
IPC分类号： H03K19/0175
CPC分类号： H04L25/028
摘要： A bus driver circuit for driving a bus voltage is provided. The bus driver circuit comprises: a bus line output (CANL) the bus voltage of which is driven by the bus driver circuit; a first transistor (M1) having a gate, the voltage at the gate of the first transistor (M1) determining the bus voltage at the bus line output (CANL); a first capacitor (C1) connected to the gate of the first transistor (M1) for driving the voltage at the gate of the first transistor (M1); a first switch (S1) connecting/disconnecting the first capacitor (C1) to a first voltage source (Vgm) via a first RC network comprising at least one resistor and at least one capacitor; and a second switch (S2) connecting/disconnecting the first capacitor (C1) to a predetermined fixed potential (GND 2) for discharging the first capacitor (C1) via a second RC network comprising at least one resistor and at least one capacitor. The first switch (S1) and the second switch (S2) are complementarily driven by a signal (TxD) on a data line.
摘要翻译： 提供用于驱动总线电压的总线驱动电路。 总线驱动电路包括：母线电压由总线驱动电路驱动的总线输出（CANL）; 具有栅极的第一晶体管（M1），第一晶体管（M1）的栅极处的电压确定总线输出端（CANL）处的总线电压; 连接到第一晶体管（M1）的栅极的第一电容器（C1），用于驱动第一晶体管（M1）的栅极处的电压; 经由包括至少一个电阻器和至少一个电容器的第一RC网络将第一电容器（C1）连接/断开到第一电压源（Vgm）的第一开关（S1） 以及通过包括至少一个电阻器和至少一个电容器的第二RC网络将第一电容器（C1）连接/断开到预定固定电位（GND2）以用于对第一电容器（C1）进行放电的第二开关（S2）。 第一开关（S1）和第二开关（S2）由数据线上的信号（TxD）互补地驱动。
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公开(公告)号：US08659344B2
公开(公告)日：2014-02-25
申请号：US13144337
申请日：2010-01-13
IPC分类号： H03K17/16
CPC分类号： G05F1/565
摘要： A power supply regulator circuit uses a feedback loop to control current through a first output transistor from a power supply input to a regulated power supply output. The first output transistor is included in an integrated circuit. In order to avoid heating of the integrated circuit in excess of an acceptable level due to permanent supply of a high current through the first transistor, current through a second output transistor in parallel with the first transistor, but outside the integrated circuit is raised when it is detected that the current through the first output transistor exceeds a threshold level. The second output transistor outside the integrated circuit serves to take over supply of a part of the power supply current from first output transistor inside integrated circuit, when long term supply of that part from first output transistor would lead to undesirable heating of the integrated circuit. During a limited time interval a first transistor current above the threshold level is acceptable. During this time interval the current through the second output transistor is raised slowly in order to avoid unpredictable stability problems and the generation of excessive power supply noise.
摘要翻译： 电源调节器电路使用反馈回路来控制从电源输入到稳压电源输出的第一输出晶体管的电流。 第一输出晶体管包含在集成电路中。 为了避免由于通过第一晶体管的高电流的永久供应而使集成电路的加热超过可接受的电平，通过与第一晶体管并联的第二输出晶体管，但是当集成电路的外部集成 检测到通过第一输出晶体管的电流超过阈值电平。 集成电路外部的第二输出晶体管用于从集成电路内部的第一输出晶体管接收一部分电源电流，当来自第一输出晶体管的该部分的长期供应将导致集成电路的不期望的加热时。 在有限的时间间隔内，高于阈值电平的第一晶体管电流是可接受的。 在该时间间隔期间，缓慢升高通过第二输出晶体管的电流，以避免不可预测的稳定性问题和产生过大的电源噪声。
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公开(公告)号：US20130281033A1
公开(公告)日：2013-10-24
申请号：US13454815
申请日：2012-04-24
申请人： Peter Gerard Steeneken , Maarten Jacobus Swanenberg , Henk Boezen , Gerhard Koops , Frans Bontekoe , Reinout Woltjer
发明人： Peter Gerard Steeneken , Maarten Jacobus Swanenberg , Henk Boezen , Gerhard Koops , Frans Bontekoe , Reinout Woltjer
IPC分类号： H04B1/44
摘要： One or more embodiments provide circuitry for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The embodiments utilize capacitive structures having increased breakdown voltage in comparison to previous parallel plate implementations. The capacitive isolation is provided by parallel plate capacitive structures, each implemented to have parallel plates of different horizontal sizes. Due to the difference in horizontal size, edges of the parallel plates, where electric fields are the strongest, are laterally offset from the region where the parallel plates overlap. As a result, breakdown voltage between the parallel plates is increased.
摘要翻译： 一个或多个实施例提供用于使用电容耦合在不同电压域中工作的电路之间的信号的隔离和通信的电路。 与先前的平行板实现相比，这些实施例利用具有增加的击穿电压的电容结构。 电容隔离由平行板电容结构提供，每个电容结构被实现为具有不同水平尺寸的平行板。 由于水平尺寸的差异，电场最强的平行板的边缘与平行板重叠的区域横向偏移。 结果，平行板之间的击穿电压增加。
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