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    DETERMINING ALLOWABLE ANTENNA AREA AS FUNCTION OF TOTAL GATE INSULATOR AREA FOR SOI TECHNOLOGY
    1.
    发明申请
    DETERMINING ALLOWABLE ANTENNA AREA AS FUNCTION OF TOTAL GATE INSULATOR AREA FOR SOI TECHNOLOGY 失效
    确定允许的天线区域作为SOI技术的总门绝缘体区域的功能

    公开(公告)号：US20090158230A1

    公开(公告)日：2009-06-18

    申请号：US11955653

    申请日：2007-12-13

    申请人： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

    发明人： Henry A. Bonges, III ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

    摘要翻译： 公开了一种确定绝缘体上半导体（SOI）技术的允许天线极限的方法。 在一个实施例中，该方法可以包括：确定门上的天线面积; 确定源/漏极上的天线面积; 确定栅极和源极/漏极网之间的总栅极绝缘体面积; 并且计算作为网之间的总门绝缘体面积的函数的可允许天线面积，使得允许较大的总天线面积用于网之间较大的总栅极绝缘体面积。

    Determining allowance antenna area as function of total gate insulator area for SOI technology
    2.
    发明授权
    Determining allowance antenna area as function of total gate insulator area for SOI technology 失效
    确定允许天线面积作为SOI技术的总栅极绝缘体面积的函数

    公开(公告)号：US07712057B2

    公开(公告)日：2010-05-04

    申请号：US11955653

    申请日：2007-12-13

    申请人： Henry A. Bonges ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

    发明人： Henry A. Bonges ,  Terence B. Hook ,  William F. Pokorny ,  Jeffrey S. Zimmerman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

    摘要翻译： 公开了一种确定绝缘体上半导体（SOI）技术的允许天线极限的方法。 在一个实施例中，该方法可以包括：确定门上的天线面积; 确定源/漏极上的天线面积; 确定栅极和源极/漏极网之间的总栅极绝缘体面积; 并且计算作为网之间的总门绝缘体面积的函数的可允许天线面积，使得允许较大的总天线面积用于网之间较大的总栅极绝缘体面积。

    STRUCTURE AND METHOD FOR REDUCING SUSCEPTIBILITY TO CHARGING DAMAGE IN SOI DESIGNS
    3.
    发明申请
    STRUCTURE AND METHOD FOR REDUCING SUSCEPTIBILITY TO CHARGING DAMAGE IN SOI DESIGNS 审中-公开
    用于降低SOI设计中对充电损害的可靠性的结构和方法

    公开(公告)号：US20070271540A1

    公开(公告)日：2007-11-22

    申请号：US11383565

    申请日：2006-05-16

    申请人： Chung-Ping Eng ,  Henry A. Bonges ,  Jeffrey S. Zimmerman ,  Terence B. Hook

    发明人： Chung-Ping Eng ,  Henry A. Bonges ,  Jeffrey S. Zimmerman ,  Terence B. Hook

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5063 ,  H01L27/0251

    摘要： Disclosed is a protection circuit for an integrated circuit device, wherein said protection circuit comprises: a first element connected to a gate of a first FET device; and a second element connected to a gate of a second FET device, wherein a drain/source of the first FET device and a drain/source of the second FET device are connected to a higher level connector and wherein the higher level connector eliminates a damaging current path between the first element and the second element.

    摘要翻译： 公开了一种用于集成电路器件的保护电路，其中所述保护电路包括：连接到第一FET器件的栅极的第一元件; 以及连接到第二FET器件的栅极的第二元件，其中所述第一FET器件的漏极/源极和所述第二FET器件的漏极/源极连接到较高级别的连接器，并且其中所述较高级连接器消除了损坏 第一元件和第二元件之间的电流路径。

    Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
    4.
    发明授权
    Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage 有权
    评估SOI设计和结构中充电损害潜力的方法，以消除损坏的可能性

    公开(公告)号：US07132318B2

    公开(公告)日：2006-11-07

    申请号：US11003988

    申请日：2004-12-04

    申请人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

    发明人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

    IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L27/0251

    摘要： Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

    摘要翻译： 公开了一种用于改变具有绝缘体上硅（SOI）晶体管的集成电路设计的方法和结构。 该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别可能在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于 电网的跟踪），以及在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。 或者，方法/结构提供通过串联装置连接补偿导体。

    Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
    5.
    发明授权
    Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage 失效
    评估SOI设计和结构中充电损害潜力的方法，以消除损坏的可能性

    公开(公告)号：US07067886B2

    公开(公告)日：2006-06-27

    申请号：US10605888

    申请日：2003-11-04

    申请人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

    发明人： Henry A. Bonges, III ,  David L. Harmon ,  Terence B. Hook ,  Wing L. Lai

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0251

    摘要： A method and structure alters an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.

    摘要翻译： 一种方法和结构改变具有硅绝缘体（SOI）晶体管的集成电路设计。 该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于 跟踪电网），并且在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。 或者，方法/结构提供通过串联装置连接补偿导体。

    IMMUNITY TO CHARGING DAMAGE IN SILICON-ON-INSULATOR DEVICES
    10.
    发明申请
    IMMUNITY TO CHARGING DAMAGE IN SILICON-ON-INSULATOR DEVICES 审中-公开
    无铅电绝缘子器件中的充电器损坏

    公开(公告)号：US20090094567A1

    公开(公告)日：2009-04-09

    申请号：US11869176

    申请日：2007-10-09

    申请人： Chung-Ping Eng ,  Terence B. Hook ,  Jeffrey S. Zimmerman

    发明人： Chung-Ping Eng ,  Terence B. Hook ,  Jeffrey S. Zimmerman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/60 ,  H01L2223/6677 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

    摘要： Method embodiments herein determine a connection order in which connections will be made to connect active devices to antennas within a given circuit design. The method also evaluates the possibilities that these connections to the antennas will cause charging damage in the devices that are connected to the antennas. Such possibilities are based on the connection order, the size of the antennas, and the likelihood that charges will flow from the antennas through insulators of the devices. If a significant possibility for damage exists, the method can reduce the size of the antenna.

    摘要翻译： 本文的方法实施例确定连接顺序，其中将连接有源器件连接到给定电路设计内的天线。 该方法还评估了这些与天线的连接在连接到天线的设备中将导致充电损坏的可能性。 这种可能性基于连接顺序，天线的尺寸以及电荷将从天线通过设备的绝缘体流过的可能性。 如果存在损坏的重大可能性，则该方法可以减小天线的尺寸。