公开(公告)号：US20140374918A1

公开(公告)日：2014-12-25

申请号：US14307108

申请日：2014-06-17

申请人： Heribert WEBER ,  Hartmut KUEPPERS ,  Jens Reutlingen ,  Neil DAVIES

发明人： Heribert WEBER ,  Hartmut KUEPPERS ,  Jens Reutlingen ,  Neil DAVIES

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  B81C1/00238 ,  B81C3/001 ,  B81C2203/0109 ,  B81C2203/0792 ,  G01C19/5783 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an ASIC element, vias are integrated into the CMOS processing of an ASIC substrate. The ASIC element includes an active front side in which the circuit functions are implemented. The at least one via is intended to establish an electrical connection between the active front side and the rear side of the element. The front side of the via is defined by at least one front-side trench which is completely filled, and the rear side is defined by at least one rear-side trench which is not completely filled. The rear-side trench opens into the filled front-side trench.

摘要翻译： 在ASIC元件中，通孔被集成到ASIC基板的CMOS处理中。 ASIC元件包括其中实现电路功能的主动正面。 该至少一个通孔旨在在元件的主动前侧和后侧之间建立电连接。 通孔的前侧由完全填充的至少一个前侧沟槽限定，并且后侧由未完全填充的至少一个后侧沟槽限定。 后侧沟槽穿过填充的前侧沟槽。

公开(公告)号：US20140374917A1

公开(公告)日：2014-12-25

申请号：US14307055

申请日：2014-06-17

申请人： Heribert WEBER ,  Hartmut KUEPPERS ,  Jens Reutlingen ,  Neil DAVIES

发明人： Heribert WEBER ,  Hartmut KUEPPERS ,  Jens Reutlingen ,  Neil DAVIES

IPC分类号： H01L23/538 ,  H01L25/065

CPC分类号： H01L29/0657 ,  B81C1/00238 ,  B81C2203/0118 ,  B81C2203/0792 ,  H01L23/3114 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2225/06506 ,  H01L2225/06568 ,  H01L2924/00014

摘要： A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the other; a molded upper sealing layer made of an electrically insulating casting; and an external electrical contacting of the component being implemented on the top side via at least one contact stamp which is embedded in the sealing layer so that (i) its lower end is connected to a wiring level of an element substrate and (ii) its upper end is exposed in the surface of the sealing layer.

摘要翻译： 垂直集成的混合部件以晶片级封装的形式实现，包括：至少两个元件基板，一个彼此组装; 由电绝缘铸件制成的模制上密封层; 并且所述部件的外部电接触通过嵌入在所述密封层中的至少一个接触印模在顶侧上实现，使得（i）其下端连接到元件基板的布线层，以及（ii）其 上端暴露在密封层的表面。

公开(公告)号：US20140374853A1

公开(公告)日：2014-12-25

申请号：US14307662

申请日：2014-06-18

申请人： Heribert WEBER ,  Hartmut KUEPPERS ,  Jens FREY ,  Jochen REINMUTH ,  Neil DAVIES

发明人： Heribert WEBER ,  Hartmut KUEPPERS ,  Jens FREY ,  Jochen REINMUTH ,  Neil DAVIES

IPC分类号： B81C1/00 ,  B81B3/00

CPC分类号： B81B7/0048 ,  H01L2224/16225

摘要： Measures are provided for stress decoupling between a semiconductor component and its mounting support, these measures being implementable very easily, inexpensively and in a space-saving manner, regardless of the substrate thickness of the component, and not being limited to soldered connections but instead also being usable in conjunction with other mounting and joining techniques. These measures relate to components, which include at least one electrical and/or micromechanical functionality and at least one wiring level, which is formed in a layer structure on a main surface of the component substrate, at least one mounting surface being implemented in the wiring level to establish a mechanical and/or electrical connection of the component to a support. The at least one mounting surface is spring mounted and is separated from the layer structure in at least some areas for this purpose.

摘要翻译： 提供了用于半导体部件与其安装支撑件之间的应力解耦的措施，这些措施可以非常容易地，低成本地且以节省空间的方式实现，而不管部件的基板厚度如何，而不仅限于焊接连接，而且还包括 可与其他安装和连接技术结合使用。 这些措施涉及组件，其包括至少一个电和/或微机械功能和至少一个布线层，其形成在部件基板的主表面上的层结构中，至少一个安装表面被实施在布线 以建立部件与支撑件的机械和/或电连接。 为此，至少一个安装表面是弹簧安装的，并且在至少一些区域中与层结构分离。