公开(公告)号：US07941738B2

公开(公告)日：2011-05-10

申请号：US11716396

申请日：2007-03-09

申请人： Hervé Le-Gall ,  Paul Armagnat ,  Jean-Christophe Pont

发明人： Hervé Le-Gall ,  Paul Armagnat ,  Jean-Christophe Pont

IPC分类号： G06K5/00

CPC分类号： G01R31/31725 ,  G01R31/3171 ,  G01R31/31727 ,  H04L7/0008 ,  H04L7/033

摘要： A bit detection event within a read period is characterized by sub-dividing each read period into elementary time intervals. Certain ones of the elementary intervals are selected to for a window and a counting operation for a number of bits detected during the intervals within the window is performed. The elementary time intervals are defined by a difference between a frequency corresponding to the read period and a bit detection timing frequency. The counting result for the intervals in the window over several consecutive read periods is statistically processed. A reduction of an integrated electronic circuit test duration results from limiting the counting operations performed to the selected elementary time intervals.

摘要翻译： 在读周期内的位检测事件的特征在于将每个读周期划分为基本时间间隔。 选择基本间隔中的某些基本间隔用于窗口，并且执行在窗口内的间隔期间检测到的多个位的计数操作。 基本时间间隔由与读取期间对应的频率与位检测定时频率之间的差定义。 统计处理在几个连续读取周期内窗口间隔的计数结果。 集成电子电路测试持续时间的减少是将执行的计数操作限制到所选择的基本时间间隔。

公开(公告)号：US20070226595A1

公开(公告)日：2007-09-27

申请号：US11716396

申请日：2007-03-09

申请人： Herve Le-Gall ,  Paul Armagnat ,  Jean-Christophe Pont

发明人： Herve Le-Gall ,  Paul Armagnat ,  Jean-Christophe Pont

IPC分类号： H03M13/00

CPC分类号： G01R31/31725 ,  G01R31/3171 ,  G01R31/31727 ,  H04L7/0008 ,  H04L7/033

摘要： A bit detection event within a read period is characterized by sub-dividing each read period into elementary time intervals. Certain ones of the elementary intervals are selected to for a window and a counting operation for a number of bits detected during the intervals within the window is performed. The elementary time intervals are defined by a difference between a frequency corresponding to the read period and a bit detection timing frequency. The counting result for the intervals in the window over several consecutive read periods is statistically processed. A reduction of an integrated electronic circuit test duration results from limiting the counting operations performed to the selected elementary time intervals.

摘要翻译： 在读周期内的位检测事件的特征在于将每个读周期划分为基本时间间隔。 选择基本间隔中的某些基本间隔用于窗口，并且执行在窗口内的间隔期间检测到的多个位的计数操作。 基本时间间隔由与读取期间对应的频率与位检测定时频率之间的差定义。 统计处理在几个连续读取周期内窗口间隔的计数结果。 集成电子电路测试持续时间的减少是将执行的计数操作限制到所选择的基本时间间隔。

公开(公告)号：US07739566B2

公开(公告)日：2010-06-15

申请号：US11698249

申请日：2007-01-24

申请人： Paul Armagnat

发明人： Paul Armagnat

IPC分类号： G01R31/28 ,  G06F3/00

CPC分类号： G01R31/318555

摘要： An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated to the state machine to the devices relating to scan testing. The state machine supports a plurality of data transfer protocols. The choice of the protocol to be used is made as a function of a signal received on the input pin. Responsive to an input pin signal, the state machine enters an operational mode wherein scan test programming data is serially received at the input pin and communicated to the devices which facilitate scan testing. More specifically, the scan test programming data is serially communicated to a scan test register, where the data is output in parallel to the scan test device.

摘要翻译： 电子电路包括一组便于扫描测试电子电路的至少一部分的装置。 这些设备包括扫描测试设备。 电路还包括状态机，其操作以将数据从专用于状态机的电路的输入引脚传送到与扫描测试有关的设备。 状态机支持多个数据传输协议。 要使用的协议的选择是根据在输入引脚上接收的信号的函数。 响应于输入引脚信号，状态机进入操作模式，其中扫描测试编程数据在输入引脚处串行接收并传送到便于扫描测试的器件。 更具体地，扫描测试编程数据被串行地传送到扫描测试寄存器，其中数据与扫描测试设备并行输出。

公开(公告)号：US20120161802A1

公开(公告)日：2012-06-28

申请号：US13338053

申请日：2011-12-27

申请人： Philippe Lebourg ,  Paul Armagnat ,  Thomas Droniou

发明人： Philippe Lebourg ,  Paul Armagnat ,  Thomas Droniou

IPC分类号： G01R31/00

CPC分类号： G01R31/318572

摘要： A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

摘要翻译： 用于集成电路的扫描测试的方法包括电路本身执行的以下步骤：在电路接通电源时，观察施加到使用引脚的位序列，其被配置为以外部速率从外部接收串行数据 时钟信号施加到时钟引脚; 当比特序列被识别为测试初始化​​序列时，以测试模式配置电路; 在移位寄存器配置中连接电路的锁存器，并且连接用于从使用引脚串联接收测试矢量的移位寄存器; 将使用引脚的传输方向切换到输出模式，以便以时钟信号的速率提供给外部串行数据; 并将移位寄存器连接到使用引脚上，作为测试结果集合提供其内容。

公开(公告)号：US08928340B2

公开(公告)日：2015-01-06

申请号：US13338053

申请日：2011-12-27

申请人： Philippe Lebourg ,  Paul Armagnat ,  Thomas Droniou

发明人： Philippe Lebourg ,  Paul Armagnat ,  Thomas Droniou

IPC分类号： G01R31/26 ,  G01R31/3185

CPC分类号： G01R31/318572

摘要： A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

摘要翻译： 用于集成电路的扫描测试的方法包括电路本身执行的以下步骤：在电路接通电源时，观察施加到使用引脚的位序列，其被配置为以外部速率从外部接收串行数据 时钟信号施加到时钟引脚; 当比特序列被识别为测试初始化​​序列时，以测试模式配置电路; 在移位寄存器配置中连接电路的锁存器，并且连接用于从使用引脚串联接收测试矢量的移位寄存器; 将使用引脚的传输方向切换到输出模式，以便以时钟信号的速率提供给外部串行数据; 并将移位寄存器连接到使用引脚上，作为测试结果集合提供其内容。

公开(公告)号：US07661040B2

公开(公告)日：2010-02-09

申请号：US10075113

申请日：2002-02-13

申请人： Marc Beaujoin ,  Thomas Alofs ,  Paul Armagnat

发明人： Marc Beaujoin ,  Thomas Alofs ,  Paul Armagnat

IPC分类号： G11C29/00 ,  G01R31/28

CPC分类号： G11C29/003 ,  G11C29/38

摘要： The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

摘要翻译： 顺序访问存储器阵列能够存储每个n位的p个字。 每个由n个测试位组成的这些p个测试字被写入存储器阵列中，p个测试字被顺序提取，并且对于每个当前提取的单词，组成它们的n个测试位被顺序地与n个相应的预期数据位进行比较 提取下一个测试字。

公开(公告)号：US20070260953A1

公开(公告)日：2007-11-08

申请号：US11698249

申请日：2007-01-24

申请人： Paul Armagnat

发明人： Paul Armagnat

IPC分类号： G01R31/28

CPC分类号： G01R31/318555

摘要： An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated to the state machine to the devices relating to scan testing. The state machine supports a plurality of data transfer protocols. The choice of the protocol to be used is made as a function of a signal received on the input pin. Responsive to an input pin signal, the state machine enters an operational mode wherein scan test programming data is serially received at the input pin and communicated to the devices which facilitate scan testing. More specifically, the scan test programming data is serially communicated to a scan test register, where the data is output in parallel to the scan test device.

摘要翻译： 电子电路包括一组便于扫描测试电子电路的至少一部分的装置。 这些设备包括扫描测试设备。 电路还包括状态机，其操作以将数据从专用于状态机的电路的输入引脚传送到与扫描测试有关的设备。 状态机支持多个数据传输协议。 要使用的协议的选择是根据在输入引脚上接收的信号的函数。 响应于输入引脚信号，状态机进入操作模式，其中扫描测试编程数据在输入引脚处串行接收并传送到便于扫描测试的器件。 更具体地，扫描测试编程数据被串行地传送到扫描测试寄存器，其中数据与扫描测试设备并行输出。