公开(公告)号：US20160216912A1

公开(公告)日：2016-07-28

申请号：US15089730

申请日：2016-04-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Aniruddha Nagendran Udipi ,  Niladrish Chatterjee ,  Rajeev Balasubramonian ,  Alan Lynn Davis ,  Norman Paul Jouppi

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1088 ,  G06F12/0802 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/3042 ,  G06F2212/305 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4082 ,  Y02D10/13

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition the example apparatus includes a column decoder (606) to selectively activate a portion of the raw based on the column address and the signal asserted on the wordline.

Abstract translation: 所公开的示例性装置包括用于将对应于行（608）的行地址存储在存储器阵列（602）中的行地址寄存器（412）。 示例性装置还包括耦合到行地址寄存器的行解码器（604），用于在存储器接收列地址之后，在行的字线（704）上断言信号。 另外，示例性装置包括列解码器（606），用于基于列地址和在字线上断言的信号选择性地激活原始部分的一部分。

公开(公告)号：US09846550B2

公开(公告)日：2017-12-19

申请号：US15089730

申请日：2016-04-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Aniruddha Nagendran Udipi ,  Niladrish Chatterjee ,  Rajeev Balasubramonian ,  Alan Lynn Davis ,  Norman Paul Jouppi

IPC: G06F11/10 ,  G06F3/06 ,  G11C5/04 ,  G11C8/12 ,  G11C11/408 ,  G11C7/10 ,  G06F12/0893 ,  G06F12/0802

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1088 ,  G06F12/0802 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/3042 ,  G06F2212/305 ,  G11C5/04 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4082 ,  Y02D10/13

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.