公开(公告)号：US10216659B2

公开(公告)日：2019-02-26

申请号：US15314605

申请日：2014-05-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jim W Brainard ,  Hubert E Brinkmann, Jr. ,  Kevin T Lim ,  Mitchel E Wright ,  Raghavan V Venugopal ,  Reza M Bacchus

IPC: G06F13/00 ,  G06F13/16 ,  G11C5/04 ,  G06F13/40 ,  G11C29/04 ,  G06F17/50

Abstract: An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.

公开(公告)号：US20170199831A1

公开(公告)日：2017-07-13

申请号：US15314605

申请日：2014-05-30

Applicant: Hewlett-Packard Enterprise Development LP

Inventor： Jim W. Brainard ,  Hubert E Brinkmann ,  Kevin T Lim ,  Mitchel E Wright ,  Raghavan V Venugopal ,  Reza M Bacchus

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1689 ,  G06F13/1694 ,  G06F13/4068 ,  G06F17/5054 ,  G06F2217/14 ,  G11C5/04 ,  G11C2029/0409

Abstract: An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.

公开(公告)号：US10453516B2

公开(公告)日：2019-10-22

申请号：US15899514

申请日：2018-02-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M Bacchus ,  Melvin K Benedict ,  Stephen F Contreras ,  Eric L Pope ,  Chi K Sides ,  Chun-Pin Huang

IPC: G11C5/06 ,  G11C5/10 ,  G11C11/4074 ,  G11C5/14 ,  G11C5/04

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.