公开(公告)号：US07303964B2

公开(公告)日：2007-12-04

申请号：US11113509

申请日：2005-04-25

申请人： Hidehiko Shiraiwa ,  Mark Randolph ,  Yu Sun

发明人： Hidehiko Shiraiwa ,  Mark Randolph ,  Yu Sun

IPC分类号： H01L21/336

CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573

摘要： Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer dielectric-charge trapping-dielectric stack 420 in a periphery region 406 of the wafer 402, thereby defining a multi-layer dielectric-charge trapping-dielectric stack 420 in a core region 404 of the wafer 402. The method 300 further comprises forming 314 a gate dielectric layer 426 over the periphery region 406 of the substrate 408, forming 316 a first polysilicon layer 428 over the multi-layer dielectric-charge trapping-dielectric stack 420 in the core region 402 and the gate dielectric 426 in the periphery region 406 , then concurrently forming 318 an isolation trench 438 in the substrate 408 in the core region 404 and in the periphery region 406. Thereafter, the isolation trenches are filled 326 with a dielectric material 446, and a second polysilicon layer 452 that is formed 332 over the first polysilicon layer 428 and the filled trenches 438, forming an self-aligned STI structure 446. The method 300 avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.

摘要翻译： 公开了用于在多位SONOS闪存器件中制造浅隔离沟槽和结构的方法300和350。 一个方法方面300包括在晶片402的衬底408（例如，ONO堆叠420）上形成310多层介电电荷俘获 - 电介质堆叠420，去除312多层介电电荷俘获 - 电介质堆叠420 在晶片402的外围区域406中，由此在晶片402的芯区域404中限定多层介电电荷捕获 - 电介质叠层420。 方法300还包括在衬底408的外围区域406上形成314栅极电介质层426，在芯区域402中的多层介电电荷捕获 - 电介质堆叠层420上形成316第一多晶硅层428，并且栅极 在外围区域406中的电介质426，然后同时在芯区域404和周边区域406中的衬底408中形成318隔离沟槽438。 此后，绝缘沟槽用介电材料446填充326，第二多晶硅层452在第一多晶硅层428和填充沟槽438上形成332，形成自对准STI结构446。 方法300避免在外围区域的STI边缘处的ONO残余桁条，减少有源区域损耗，减少STI边缘处的外围栅极氧化物和ONO的稀化，并且由于减少的热处理步骤，在隔离注入期间减少掺杂剂扩散。

公开(公告)号：US20060240635A1

公开(公告)日：2006-10-26

申请号：US11113509

申请日：2005-04-25

申请人： Hidehiko Shiraiwa ,  Mark Randolph ,  Yu Sun

发明人： Hidehiko Shiraiwa ,  Mark Randolph ,  Yu Sun

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573

摘要： Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer dielectric-charge trapping-dielectric stack 420 in a periphery region 406 of the wafer 402, thereby defining a multi-layer dielectric-charge trapping-dielectric stack 420 in a core region 404 of the wafer 402. The method 300 further comprises forming 314 a gate dielectric layer 426 over the periphery region 406 of the substrate 408, forming 316 a first polysilicon layer 428 over the multi-layer dielectric-charge trapping-dielectric stack 420 in the core region 402 and the gate dielectric 426 in the periphery region 406 , then concurrently forming 318 an isolation trench 438 in the substrate 408 in the core region 404 and in the periphery region 406. Thereafter, the isolation trenches are filled 326 with a dielectric material 446, and a second polysilicon layer 452 that is formed 332 over the first polysilicon layer 428 and the filled trenches 438, forming an self-aligned STI structure 446. The method 300 avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.

摘要翻译： 公开了用于在多位SONOS闪存器件中制造浅隔离沟槽和结构的方法300和350。 一个方法方面300包括在晶片402的衬底408（例如，ONO堆叠420）上形成310多层介电电荷俘获 - 电介质堆叠420，去除312多层介电电荷俘获 - 电介质堆叠420 在晶片402的外围区域406中，由此在晶片402的芯区域404中限定多层介电电荷捕获 - 电介质叠层420.方法300还包括在周边区域314上形成314栅极电介质层426 406，在芯区域402中的多层介电 - 电荷俘获 - 电介质堆叠层420和周边区域406中的栅极电介质426之间形成316第一多晶硅层428，然后同时形成318隔离沟槽438 在核心区域404和外围区域406中的衬底408中。此后，隔离沟槽用介电材料446填充326，第二多晶硅层452形成为332o 形成第一多晶硅层428和填充沟槽438，形成自对准STI结构446.方法300避免在外围区域的STI边缘处的ONO残余桁条，减少有源区域损耗，减少外围栅极氧化物的稀化和 ONO在STI边缘，并且由于减少的热处理步骤，在隔离注入期间减少掺杂剂扩散。

公开(公告)号：US07492001B2

公开(公告)日：2009-02-17

申请号：US11086310

申请日：2005-03-23

申请人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

发明人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

IPC分类号： H01L29/788 ,  H01L29/72

CPC分类号： H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

摘要翻译： 存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。 存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。 存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极 形成在电介质材料层上。

公开(公告)号：US07855114B2

公开(公告)日：2010-12-21

申请号：US12351553

申请日：2009-01-09

申请人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

发明人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

IPC分类号： H01L21/336 ,  H01L29/778

CPC分类号： H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

摘要翻译： 存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。 存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。 存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极 形成在电介质材料层上。

公开(公告)号：US07339222B1

公开(公告)日：2008-03-04

申请号：US11416551

申请日：2006-05-03

申请人： Meng Ding ,  Hidehiko Shiraiwa ,  Mark Randolph

发明人： Meng Ding ,  Hidehiko Shiraiwa ,  Mark Randolph

IPC分类号： H01L27/108

CPC分类号： H01L27/115 ,  H01L27/11517 ,  Y10S257/905

摘要： According to one exemplary embodiment, a method for fabricating a memory array includes forming a number of trenches in a substrate, where the trenches determine a number of wordline regions in the substrate, where each of the wordline regions is situated between two adjacent trenches, and where each of the wordline regions have a wordline region width. The memory array can be a flash memory array. The method further includes forming a number of bitlines in the substrate, where the bitlines are situated perpendicular to the trenches. The method further includes forming a dielectric region in each of the trenches. The method further includes forming a dielectric stack over the bitlines, wordline regions, and trenches. The method further includes forming a number of wordlines, where each wordline is situated over one of the wordline regions. The wordline region width determines an active wordline width of each of the wordlines.

摘要翻译： 根据一个示例性实施例，一种用于制造存储器阵列的方法包括在衬底中形成多个沟槽，其中沟槽确定衬底中的多个字线区域，其中每个字线区域位于两个相邻的沟槽之间，以及 其中每个字线区域具有字线区域宽度。 存储器阵列可以是闪存阵列。 该方法还包括在衬底中形成多个位线，其中位线垂直于沟槽定位。 该方法还包括在每个沟槽中形成电介质区域。 该方法还包括在位线，字线区域和沟槽之间形成电介质叠层。 该方法还包括形成多个字线，其中每个字线位于一个字线区域上。 字线区域宽度决定每个字线的有效字线宽度。

公开(公告)号：US07381620B1

公开(公告)日：2008-06-03

申请号：US11371023

申请日：2006-03-09

申请人： Boon-Yong Ang ,  Hidehiko Shiraiwa ,  Simon S. Chan ,  Harpreet K. Sachar ,  Mark Randolph

发明人： Boon-Yong Ang ,  Hidehiko Shiraiwa ,  Simon S. Chan ,  Harpreet K. Sachar ,  Mark Randolph

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L21/3144 ,  H01L21/3162 ,  H01L27/11568

摘要： A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.

摘要翻译： 一种方法包括在包含氧的处理室中形成半导体器件的至少一部分，并从处理室中去除基本上所有的氧。 该方法还包括在处理室内形成半导体器件的剩余部分而不存在氧气。

公开(公告)号：US07365389B1

公开(公告)日：2008-04-29

申请号：US11008233

申请日：2004-12-10

申请人： Joong Jeon ,  Wei Zheng ,  Mark Randolph ,  Meng Ding ,  Hidehiko Shiraiwa

发明人： Joong Jeon ,  Wei Zheng ,  Mark Randolph ,  Meng Ding ,  Hidehiko Shiraiwa

IPC分类号： H01L29/792

CPC分类号： H01L29/513 ,  H01L29/792

摘要： A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory device may be efficiently erased using Fowler-Nordheim tunneling.

摘要翻译： 半导体存储器件可以包括介于电荷存储层和控制栅之间的高K，高势垒高电介质材料的隔间电介质层。 利用这种隔间高K，高势垒高电介质就位，可以使用Fowler-Nordheim隧道有效地擦除存储器件。

公开(公告)号：US20060216888A1

公开(公告)日：2006-09-28

申请号：US11086310

申请日：2005-03-23

申请人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

发明人： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

摘要： A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

公开(公告)号：US07071538B1

公开(公告)日：2006-07-04

申请号：US11008263

申请日：2004-12-10

申请人： Hidehiko Shiraiwa ,  Harpreet K. Sachar ,  Mark Randolph ,  Wei Zheng

发明人： Hidehiko Shiraiwa ,  Harpreet K. Sachar ,  Mark Randolph ,  Wei Zheng

IPC分类号： H01L21/31

CPC分类号： H01L21/28282 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/3162 ,  H01L21/31662 ,  H01L29/518

摘要： A semiconductor device includes a substrate that further includes source, drain and channel regions. The device may further include a bottom oxide layer formed upon the substrate, a charge storage layer formed upon the bottom oxide layer, and a steam oxide layer thermally grown upon the charge storage layer. The device may also include an alumina oxide layer formed upon the steam oxide layer and a gate electrode formed upon the alumina oxide layer.

摘要翻译： 半导体器件包括还包括源极，漏极和沟道区的衬底。 该器件还可以包括形成在衬底上的底部氧化物层，形成在底部氧化物层上的电荷存储层和在电荷存储层上热生长的蒸汽氧化物层。 该装置还可以包括形成在蒸汽氧化物层上的氧化铝层和形成在氧化铝层上的栅电极。

公开(公告)号：US06900085B2

公开(公告)日：2005-05-31

申请号：US09891885

申请日：2001-06-26

申请人： Mark T. Ramsbey ,  Michael Fliesler ,  Mark Randolph ,  Mimi Qian ,  Yu Sun

发明人： Mark T. Ramsbey ,  Michael Fliesler ,  Mark Randolph ,  Mimi Qian ,  Yu Sun

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/7833 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.

摘要翻译： 本发明的一个方面提供了一种用于形成具有ESD保护晶体管的IC器件的方法。 根据本发明的一个方面，ESD保护晶体管具有轻掺杂，然后在形成间隔物之后，进行重掺杂。 具有间隔物的重掺杂可以降低薄层电阻，增强晶体管的双极效应，降低晶体管的电容，并降低结击穿电压，而不会导致短沟道效应。 因此，本发明提供了紧凑，高灵敏度和快速切换的ESD保护晶体管。 间隔物可以与其他晶体管的间隔物同时形成，例如器件的外围区域中的其它晶体管。