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    ESD implant following spacer deposition
    1.
    发明授权
    ESD implant following spacer deposition 有权
    间隔物沉积后的ESD植入

    公开(公告)号：US06900085B2

    公开(公告)日：2005-05-31

    申请号：US09891885

    申请日：2001-06-26

    申请人： Mark T. Ramsbey ,  Michael Fliesler ,  Mark Randolph ,  Mimi Qian ,  Yu Sun

    发明人： Mark T. Ramsbey ,  Michael Fliesler ,  Mark Randolph ,  Mimi Qian ,  Yu Sun

    IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L21/8234

    CPC分类号： H01L29/7833 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.

    摘要翻译： 本发明的一个方面提供了一种用于形成具有ESD保护晶体管的IC器件的方法。 根据本发明的一个方面，ESD保护晶体管具有轻掺杂，然后在形成间隔物之后，进行重掺杂。 具有间隔物的重掺杂可以降低薄层电阻，增强晶体管的双极效应，降低晶体管的电容，并降低结击穿电压，而不会导致短沟道效应。 因此，本发明提供了紧凑，高灵敏度和快速切换的ESD保护晶体管。 间隔物可以与其他晶体管的间隔物同时形成，例如器件的外围区域中的其它晶体管。

    Diode fabrication for ESD/EOS protection
    2.
    发明授权
    Diode fabrication for ESD/EOS protection 有权
    用于ESD / EOS保护的二极管制造

    公开(公告)号：US06770938B1

    公开(公告)日：2004-08-03

    申请号：US10050394

    申请日：2002-01-16

    申请人： Michael Fliesler ,  Mark Ramsbey ,  Mark Randolph ,  Ian Morgan ,  Timothy Thurgate ,  Paohua Kuo ,  David M. Rogers

    发明人： Michael Fliesler ,  Mark Ramsbey ,  Mark Randolph ,  Ian Morgan ,  Timothy Thurgate ,  Paohua Kuo ,  David M. Rogers

    IPC分类号： H01L2362

    CPC分类号： H01L27/0255

    摘要： An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply VCC and a second power supply VSS. An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply VCC used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.

    摘要翻译： 为集成电路提供ESD保护装置。 ESD保护装置包括由二极管形成并耦合在第一电源VCC和第二电源VSS之间的电源钳位装置。 还提供一种输入保护装置，其由耦合在输入焊盘和第一电源之间的二极管和耦合在输入焊盘和第二电源之间的第二二极管形成。 二极管具有调整的反向击穿电压，其高于用于为驱动集成电路的核心内的电路的外围电路供电的电压源VCC。 调整的反向击穿电压也低于在外围电路中使用的栅极氧化物层的击穿电压。

    Method and apparatus for achieving bond pad crater sensing and ESD protection integrated circuit products
    4.
    发明授权
    Method and apparatus for achieving bond pad crater sensing and ESD protection integrated circuit products 失效
    用于在集成电路产品中实现焊盘凹坑感测和ESD保护的方法和装置

    公开(公告)号：US06395568B1

    公开(公告)日：2002-05-28

    申请号：US09624665

    申请日：2000-07-25

    申请人： Richard C. Blish ,  Colin D. Hatchard ,  Ian Morgan ,  Michael Fliesler

    发明人： Richard C. Blish ,  Colin D. Hatchard ,  Ian Morgan ,  Michael Fliesler

    IPC分类号： H01L2166

    CPC分类号： H01L22/34 ,  H01L22/12 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2224/48463 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/00014

    摘要： Method for bond pad crater jeopardy identification in integrated circuits, and apparatus which performs the method. The gate or gates of a transistor or transistors of an ESD device are formed under each bond pad in the integrated circuit device. Connected to the transistor is circuitry for determimg the electrical, and hence mechanical, integrity of the transistor. A reduction in current through the transistor, by reason of microcrack formation in the several layers under the transistor causing a gate or gates of the transistor to crack and fail, may detected, Location of at least a portion of the ESD device, for example the above transistor, reduces overall chip area by increasing device density.

    摘要翻译： 集成电路中焊盘火山口危险识别方法，以及执行该方法的装置。 晶体管的栅极或ESD器件的晶体管的栅极形成在集成电路器件中的每个接合焊盘下方。 连接到晶体管是用于确定晶体管的电而且因此机械的完整性的电路。 通过晶体管的电流减小，由于在晶体管下面的几层中的微裂纹形成导致晶体管的栅极或栅极破裂和失效，可能会检测到ESD器件的至少一部分的位置，例如 晶体管上方，通过提高器件密度来降低整体芯片面积。

    Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits
    7.
    发明授权
    Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits 失效
    光刻胶间隔物工艺简化，以消除闪存电路的标准多晶硅或氧化物隔离工艺

    公开(公告)号：US06440789B1

    公开(公告)日：2002-08-27

    申请号：US09704026

    申请日：2000-11-01

    申请人： Darlene Hamilton ,  Len Toyoshiba ,  Michael Fliesler

    发明人： Darlene Hamilton ,  Len Toyoshiba ,  Michael Fliesler

    IPC分类号： H01L218238

    CPC分类号： H01L27/11526 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/11546

    摘要： A method of manufacturing a flash memory semiconductor device that eliminates the step of forming sidewall spacers on n-channel and p-channel transistor gate structures. Resist spacers having a dimension of Gn+2Sn are formed on n-channel transistor gate structures and an N+ implant is performed to form N+ implant is performed to form N+ regions in the n-channel substrate region. Resist spacers having a dimension of Gs +2Sp are formed on p-channel transistor gate structures and a P+ implant is performed to form P+ regions in the p-channel substrate region.

    摘要翻译： 一种制造闪存半导体器件的方法，其消除了在n沟道和p沟道晶体管栅极结构上形成侧壁间隔物的步骤。 在n沟道晶体管栅极结构上形成具有Gn + 2Sn尺寸的抗蚀间隔物，并且执行N +注入以形成N +注入，以在n沟道衬底区域中形成N +区。 在p沟道晶体管栅极结构上形成具有Gs + 2Sp尺寸的抗蚀间隔物，并且执行P +注入以在p沟道衬底区域中形成P +区。