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公开(公告)号：US20050083756A1
公开(公告)日：2005-04-21
申请号：US10971115
申请日：2004-10-25
IPC分类号： H01L21/3205 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
摘要翻译： 半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a， 5b和第二连接器5c，5d。 每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。 位线沿垂直于第一方向的第二方向彼此平行布置。 第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。 第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。
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公开(公告)号：US08395932B2
公开(公告)日：2013-03-12
申请号：US12827668
申请日：2010-06-30
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
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公开(公告)号：US20070177416A1
公开(公告)日：2007-08-02
申请号：US11727040
申请日：2007-03-23
IPC分类号： G11C17/00
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
摘要翻译： 半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a， 5b和第二连接器5c，5d。 每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。 位线沿垂直于第一方向的第二方向彼此平行布置。 第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。 第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。
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公开(公告)号：US06812574B2
公开(公告)日：2004-11-02
申请号：US10190715
申请日：2002-07-09
IPC分类号： H01L2348
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
摘要翻译： 半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a，5b和第二栅极布线元件 连接器5c，5d。 每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。 位线沿垂直于第一方向的第二方向彼此平行布置。 第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。 第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。
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公开(公告)号：US20100265752A1
公开(公告)日：2010-10-21
申请号：US12827668
申请日：2010-06-30
IPC分类号： G11C5/02
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
摘要翻译： 半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a，5b和第二栅极布线元件 连接器5c，5d。 每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。 位线沿垂直于第一方向的第二方向彼此平行布置。 第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。 第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。
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公开(公告)号：US08422274B2
公开(公告)日：2013-04-16
申请号：US13296956
申请日：2011-11-15
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
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公开(公告)号：US20120063213A1
公开(公告)日：2012-03-15
申请号：US13296956
申请日：2011-11-15
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
摘要翻译： 半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a，5b和第二栅极布线元件 连接器5c，5d。 每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。 位线沿垂直于第一方向的第二方向彼此平行布置。 第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。 第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。
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公开(公告)号：US20090034317A1
公开(公告)日：2009-02-05
申请号：US12237037
申请日：2008-09-24
IPC分类号： G11C17/12
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/11 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.
摘要翻译： 半导体存储装置包括存储单元阵列，多个字线，多个位线，第一栅极布线元件3a，3b，第二栅极布线元件3c，3d，第一连接器5a，5b和第二栅极布线元件 连接器5c，5d。 每个存储单元10具有第一和第二组，其具有驱动晶体管11，负载晶体管12和存取晶体管13.字线沿着第一方向彼此平行布置。 位线沿垂直于第一方向的第二方向彼此平行布置。 第一栅极布线元件包括第一驱动晶体管的栅电极和第一负载晶体管，并且具有在相对侧具有直线的矩形形状。 第二栅极布线元件包括存取晶体管的栅电极，并且具有在相对侧具有直线的矩形形状。
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公开(公告)号：US06714478B2
公开(公告)日：2004-03-30
申请号：US10212816
申请日：2002-08-07
IPC分类号： G11C800
CPC分类号： G11C8/14 , G11C11/41 , G11C2029/1202 , G11C2029/2602
摘要： A local decoder controlling activation of each word line includes a first transistor connected between first and second nodes, a second transistor connected between a power-supply voltage and the first node, and an inverter driving a word line with the power-supply voltage or a ground voltage in accordance with the voltage of the first node. When a corresponding word line is activated, the second node is set at the ground voltage while the first transistor is turned on. In a burn-in test, a burn-in control circuit forcibly turns off the second transistor in a local decoder corresponding to a word line to be activated.
摘要翻译： 控制每个字线的激活的本地解码器包括连接在第一和第二节点之间的第一晶体管，连接在电源电压和第一节点之间的第二晶体管，以及驱动具有电源电压的字线的逆变器或 接地电压根据第一节点的电压。 当对应的字线被激活时，在第一晶体管导通的同时将第二节点设置在接地电压。 在老化测试中，老化控制电路强制地关闭对应于要被激活的字线的本地解码器中的第二晶体管。
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10.发明授权Semiconductor memory device having a capacitive plate to reduce soft errors 有权具有用于减少软错误的电容板的半导体存储器件公开(公告)号：US06891743B2
公开(公告)日：2005-05-10
申请号：US10195381
申请日：2002-07-16
IPC分类号： G11C11/41 , G11C11/412 , G11C29/00 , G11C29/04 , H01L21/8244 , H01L27/02 , H01L27/10 , H01L27/11 , G11C15/00
CPC分类号： G11C29/83 , G11C11/4125 , G11C29/832 , H01L27/0207 , H01L27/1104
摘要： A CMOS-SRAM has a plurality of full CMOS type memory cells (1) and a capacity plate (2). The memory cells (1) are two-dimensionally arranged in the row direction and in the column direction. The capacity plate 2 adds an additional capacity to nodes ND1 and ND2 for storing data in order to reduce soft errors. The capacity plate (2) is common with the plurality of memory cells (1). The capacity plates (2) are separated by every column, that is in the row direction. The capacity plate (2) is connected to a power voltage line VDD so as to simplify the voltage supplying system. When a stand-by failure occurs in the memory cell (1) of a certain column, the memory cell (1) is replaced with a redundant memory cell.
摘要翻译： CMOS-SRAM具有多个全CMOS型存储单元（1）和容量板（2）。 存储单元（1）在行方向和列方向上二维排列。 容量板2为节点ND 1和ND 2添加额外的容量以存储数据，以便减少软错误。 容量板（2）与多个存储单元（1）相同。 容量板（2）由行列方向分隔。 容量板（2）连接到电源电压线VDD，以简化供电系统。 当在某列的存储单元（1）中发生备用故障时，存储器单元（1）被替换为冗余存储单元。
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