公开(公告)号：US20100203706A1

公开(公告)日：2010-08-12

申请号：US12762600

申请日：2010-04-19

申请人： Hideto OHNUMA ,  Ryota IMAHAYASHI ,  Yoichi IIKUBO ,  Kenichiro MAKINO ,  Sho NAGAMATSU

发明人： Hideto OHNUMA ,  Ryota IMAHAYASHI ,  Yoichi IIKUBO ,  Kenichiro MAKINO ,  Sho NAGAMATSU

IPC分类号： H01L21/762

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/78654

摘要： It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.

摘要翻译： 本发明的一个目的是提供一种制造具有单晶半导体层的SOI衬底的方法，即使当具有低耐热温度的衬底如玻璃衬底或 并且进一步通过使用这种SOI衬底制造具有高可靠性的半导体器件。 将与半导体基板分离并与具有绝缘面的支撑基板接合的半导体层用电磁波照射，对半导体层的表面进行抛光处理。 半导体层的区域的至少一部分通过电磁波的照射而熔融，能够降低半导体层的晶体缺陷。 此外，半导体层的表面可以通过抛光处理被抛光和平坦化。

公开(公告)号：US20130011961A1

公开(公告)日：2013-01-10

申请号：US13539907

申请日：2012-07-02

申请人： Akihiro ISHIZUKA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Sho NAGAMATSU

发明人： Akihiro ISHIZUKA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Sho NAGAMATSU

IPC分类号： H01L21/36

CPC分类号： H01L21/02422 ,  H01L21/02488 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/3105 ,  H01L29/66969 ,  H01L29/78636 ,  H01L29/7869

摘要： An object is to provide a semiconductor device having excellent characteristics, in which a channel layer includes an oxide semiconductor with high crystallinity. In addition, a semiconductor device including a base film with improved planarity is provided. CMP treatment is performed on the base film of the transistor and plasma treatment is performed thereon after the CMP treatment, whereby the base film can have a center line average roughness Ra75 of less than 0.1 nm. The oxide semiconductor layer with high crystallinity is formed over the base film having planarity, which is obtained by the combination of the plasma treatment and the CMP treatment, thereby improving the characteristics of the semiconductor device.

摘要翻译： 目的在于提供具有优异特性的半导体器件，其中沟道层包括具有高结晶度的氧化物半导体。 此外，提供了包括具有改善的平面度的基膜的半导体器件。 在晶体管的基膜上进行CMP处理，在CMP处理之后进行等离子体处理，由此基膜的中心线平均粗糙度Ra75可以小于0.1nm。 在通过等离子体处理和CMP处理的组合获得的具有平坦度的基膜上形成具有高结晶度的氧化物半导体层，从而提高半导体器件的特性。

公开(公告)号：US20120187396A1

公开(公告)日：2012-07-26

申请号：US13355950

申请日：2012-01-23

申请人： Shunpei YAMAZAKI ,  Teruyuki FUJII ,  Sho NAGAMATSU

发明人： Shunpei YAMAZAKI ,  Teruyuki FUJII ,  Sho NAGAMATSU

IPC分类号： H01L29/786 ,  H01L21/44

CPC分类号： H01L29/7869 ,  H01L23/564 ,  H01L29/36 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78621 ,  H01L2924/0002 ,  H01L2924/00

摘要： A base insulating film is formed over a substrate. A first oxide semiconductor film is formed over the base insulating film, and then first heat treatment is performed to form a second oxide semiconductor film. Then, selective etching is performed to form a third oxide semiconductor film. An insulating film is formed over the first insulating film and the third oxide semiconductor film. A surface of the insulating film is polished to expose a surface of the third oxide semiconductor film, so that a sidewall insulating film is formed in contact with at least a side surface of the third oxide semiconductor film. Then, a source electrode and a drain electrode are formed over the sidewall insulating film and the third oxide semiconductor film. A gate insulating film and a gate electrode are formed.

摘要翻译： 在基板上形成基极绝缘膜。 在基底绝缘膜上形成第一氧化物半导体膜，然后进行第一热处理以形成第二氧化物半导体膜。 然后，进行选择性蚀刻以形成第三氧化物半导体膜。 绝缘膜形成在第一绝缘膜和第三氧化物半导体膜上。 抛光绝缘膜的表面以暴露第三氧化物半导体膜的表面，使得形成与第三氧化物半导体膜的至少侧面接触的侧壁绝缘膜。 然后，在侧壁绝缘膜和第三氧化物半导体膜上形成源电极和漏电极。 形成栅极绝缘膜和栅电极。

公开(公告)号：US20130075733A1

公开(公告)日：2013-03-28

申请号：US13609931

申请日：2012-09-11

申请人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Sho NAGAMATSU

发明人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Sho NAGAMATSU

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L21/02565 ,  H01L21/44 ,  H01L21/463 ,  H01L21/465 ,  H01L27/1225 ,  H01L27/14632 ,  H01L27/14687 ,  H01L29/04 ,  H01L29/78 ,  H01L29/7869

摘要： A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.

摘要翻译： 一分钟晶体管和微晶体管的制造方法。 源极电极层和漏极电极层各自形成在形成在覆盖半导体层的绝缘层中的对应的开口中。 源电极层的开口和漏电极层的开口分开形成两个不同的步骤。 源极电极层和漏电极层通过在绝缘层上和开口中沉积导电层而形成，然后通过抛光去除绝缘层上方的部分。 该制造方法允许稍后的源极电极和漏极电极层彼此靠近并且靠近半导体层的沟道形成区域。 这种结构导致即使在微小结构的情况下也具有高电特性和高制造成品率的晶体管。