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    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same
    6.
    发明申请
    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
    具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法

    公开(公告)号：US20080036006A1

    公开(公告)日：2008-02-14

    申请号：US11802281

    申请日：2007-05-22

    申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

    摘要翻译： 具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。 该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。 在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same
    7.
    发明授权
    Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
    具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法

    公开(公告)号：US08445968B2

    公开(公告)日：2013-05-21

    申请号：US13091327

    申请日：2011-04-21

    申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    IPC分类号： H01L21/70

    CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

    摘要翻译： 具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。 该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。 在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07728393B2

    公开(公告)日：2010-06-01

    申请号：US11492939

    申请日：2006-07-26

    申请人： Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee

    发明人： Hwa-sung Rhee ,  Tetsuji Ueno ,  Ho Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66636 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628

    摘要： A semiconductor device and method of manufacturing the semiconductor device are provided. The semiconductor device may include a semiconductor substrate, a gate insulation layer and a gate electrode, a first spacer, a second spacer, an epitaxial pattern, and/or source/drain regions. The gate insulation layer and the gate electrode may be formed on the semiconductor substrate. The first spacer may be formed on sidewalls of the gate electrode. The second spacer may be formed on sidewalls of the first spacer. The epitaxial pattern may be formed between the second spacer and the semiconductor substrate such that an outside profile of the epitaxial pattern is aligned with an outside profile of the second spacer. The source/drain regions may include primary source/drain regions that are aligned with the first spacer. The primary source/drain regions may be formed in the epitaxial pattern and the semiconductor substrate. The source/drain regions may also include secondary source/drain regions that are aligned with the second spacer and formed in the semiconductor substrate.

    摘要翻译： 提供一种制造半导体器件的半导体器件和方法。 半导体器件可以包括半导体衬底，栅极绝缘层和栅电极，第一间隔物，第二间隔物，外延图案和/或源极/漏极区域。 栅极绝缘层和栅电极可以形成在半导体衬底上。 第一间隔物可以形成在栅电极的侧壁上。 第二间隔件可以形成在第一间隔件的侧壁上。 外延图案可以形成在第二间隔物和半导体衬底之间，使得外延图案的外部轮廓与第二间隔物的外部轮廓对准。 源极/漏极区域可以包括与第一间隔物对准的主要源极/漏极区域。 初级源极/漏极区域可以形成为外延图案和半导体衬底。 源极/漏极区域还可以包括与第二间隔物对准并形成在半导体衬底中的次级源极/漏极区域。

    METHOD OF FABRICATING CMOS TRANSISTOR AND CMOS TRANSISTOR FABRICATED THEREBY
    9.
    发明申请
    METHOD OF FABRICATING CMOS TRANSISTOR AND CMOS TRANSISTOR FABRICATED THEREBY 失效
    制造CMOS晶体管和CMOS晶体管的方法

    公开(公告)号：US20080135879A1

    公开(公告)日：2008-06-12

    申请号：US12029884

    申请日：2008-02-12

    申请人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

    发明人： Dong-suk Shin ,  Hwa-sung Rhee ,  Ueno Tetsuji ,  Ho Lee ,  Seung-hwan Lee

    IPC分类号： H01L27/092

    CPC分类号： H01L29/66636 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

    摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.

    摘要翻译： 在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。 同时，通过减少所需掩模的数量来简化制造过程。 该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域 大于第二导电型MOS晶体管的有源区中的第一深度。 在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层 凹陷区域。

    Semiconductor Devices with Stressed Channel Regions and methods Forming the Same
    10.
    发明申请
    Semiconductor Devices with Stressed Channel Regions and methods Forming the Same 审中-公开
    具有强调通道区域和方法的半导体器件形成相同

    公开(公告)号：US20070057320A1

    公开(公告)日：2007-03-15

    申请号：US11426595

    申请日：2006-06-27

    申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7848 ,  H01L29/66628 ,  H01L29/66636

    摘要： A semiconductor device includes a substrate having a semiconductor channel region therein. A gate electrode is provided on the channel region. A SiGeC stress-inducing region is provided adjacent the channel region. The SiGeC region is configured to form a semiconductor junction with the channel region and induce a net mobility-enhancing stress in a portion of the channel region. The SiGeC region may have a Ge/C atomic ratio of less than about 12. The SiGeC region also has a sufficient concentration of substitutional C atoms therein to induce a net tensile stress in the portion of the channel region, which has a different lattice constant relative to the SiGeC region.

    摘要翻译： 半导体器件包括其中具有半导体沟道区的衬底。 栅电极设置在沟道区上。 在沟道区附近提供SiGeC应力诱导区。 SiGeC区域被配置为与沟道区域形成半导体结，并且在沟道区域的一部分中引起净迁移率增强应力。 SiGeC区域可以具有小于约12的Ge / C原子比.SiGeC区域还具有足够的取代C原子浓度，以在沟道区域中具有不同晶格常数的部分中的净拉伸应力 相对于SiGeC区域。