公开(公告)号：US5915179A

公开(公告)日：1999-06-22

申请号：US660479

申请日：1996-06-07

申请人： Hiroki Etou ,  Kazunori Ohno ,  Takaaki Saito ,  Naofumi Tsuchiya ,  Toshinari Utsumi

发明人： Hiroki Etou ,  Kazunori Ohno ,  Takaaki Saito ,  Naofumi Tsuchiya ,  Toshinari Utsumi

IPC分类号： H01L29/872 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/47 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L27/0629 ,  H01L29/7806 ,  H01L2224/48247 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091

摘要： In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.

摘要翻译： 在本发明中，在相同的半导体衬底上形成用作DC-DC转换器的开关器件的垂直型MOSFET和肖特基势垒二极管。 此外，肖特基势垒二极管所需的阻挡金属也形成在垂直型MOSFET的电极部分上。 此外，肖特基势垒二极管形成区域形成为具有比垂直型MOSFET形成区域低的杂质浓度。

公开(公告)号：US08148788B2

公开(公告)日：2012-04-03

申请号：US12538635

申请日：2009-08-10

申请人： Akira Suzuki ,  Naofumi Tsuchiya ,  Koujiro Kameyama

发明人： Akira Suzuki ,  Naofumi Tsuchiya ,  Koujiro Kameyama

IPC分类号： H01L21/762

CPC分类号： H01L29/8611 ,  H01L21/76229 ,  H01L29/0615 ,  H01L29/7322

摘要： The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N− type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.

摘要翻译： 本发明旨在降低制造成本和提高邻接在保护环上的PN结部分的击穿电压。 在半导体衬底的前表面上形成N-型半导体层，并在其上形成P型半导体层。 在P型半导体层上形成绝缘膜。 然后，从绝缘膜到N型半导体层的厚度方向的中间形成有多个槽，即第一槽，第二槽和第三槽。 多个槽形成为使得彼此相邻的两个凹槽中的一个更靠近电子器件即阳极电极的形状比位于该外部的另一个凹槽更浅。 然后，绝缘材料沉积在第一槽，第二槽和第三槽中。 然后将半导体衬底的层压体和层压在其上的层切割成切割线。

公开(公告)号：US20130075243A1

公开(公告)日：2013-03-28

申请号：US13608374

申请日：2012-09-10

申请人： Naofumi Tsuchiya ,  Makoto Koizumi ,  Hiroyuki Ono

发明人： Naofumi Tsuchiya ,  Makoto Koizumi ,  Hiroyuki Ono

IPC分类号： H01H13/14 ,  H03K17/975

CPC分类号： H01H13/52 ,  H01H2003/007 ,  H01H2221/044

摘要： A switch device includes: a switch; an operation section disposed to face the switch; a first resilient section that is deformed by first pressing force derived from the operation section; and a second resilient section that is brought into contact with the switch by the deformation of the first resilient section, and is deformed to activate the switch by second pressing force greater than the first pressing force.

摘要翻译： 开关装置包括：开关; 设置成面向开关的操作部; 第一弹性部，其通过从所述操作部得到的第一按压力而变形; 以及通过第一弹性部分的变形而与开关接触的第二弹性部分，并且通过大于第一按压力的第二按压力而变形以致动开关。

公开(公告)号：US08319317B2

公开(公告)日：2012-11-27

申请号：US12481292

申请日：2009-06-09

申请人： Katsuyuki Seki ,  Naofumi Tsuchiya ,  Akira Suzuki ,  Kikuo Okada

发明人： Katsuyuki Seki ,  Naofumi Tsuchiya ,  Akira Suzuki ,  Kikuo Okada

IPC分类号： H01L23/58

CPC分类号： H01L21/8222 ,  H01L21/02118 ,  H01L21/312 ,  H01L21/31662 ,  H01L27/0814 ,  H01L2924/10155

摘要： Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N− type semiconductor layer and the thermal oxide film. With the structure described above, an influence of the positive electric charges in the thermal oxide film is weakened and an extension of a depletion layer into the N− type semiconductor layer at the interface with the thermal oxide film is secured.

摘要翻译： 使用便宜的材料来解决传统的台面型半导体器件的问题，其中耐腐蚀性劣化和由与PN结相对应的台面凹槽的内壁上的绝缘膜的厚度减小引起的漏电流的发生 并且提供具有高耐压和高可靠性的台面型半导体器件及其制造方法。 在台面型半导体器件的台面槽的内壁上形成由热氧化膜制成的稳定的保护膜，以覆盖和保护PN结，形成具有负电荷的绝缘膜以填充 用热氧化膜覆盖的台面槽，使得在N-型半导体层和热氧化膜之间的界面处不容易形成电子蓄积层。 利用上述结构，确保了热氧化膜中的正电荷的影响，确保了与热氧化膜的界面处的耗尽层向N型半导体层的延伸。

公开(公告)号：US20100052090A1

公开(公告)日：2010-03-04

申请号：US12538635

申请日：2009-08-10

申请人： Akira Suzuki ,  Naofumi Tsuchiya ,  Koujiro Kameyama

发明人： Akira Suzuki ,  Naofumi Tsuchiya ,  Koujiro Kameyama

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L29/8611 ,  H01L21/76229 ,  H01L29/0615 ,  H01L29/7322

摘要： The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N− type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.

摘要翻译： 本发明旨在降低制造成本和提高邻接在保护环上的PN结部分的击穿电压。 在半导体衬底的前表面上形成N-型半导体层，并在其上形成P型半导体层。 在P型半导体层上形成绝缘膜。 然后，从绝缘膜到N型半导体层的厚度方向的中间形成有多个槽，即第一槽，第二槽和第三槽。 多个槽形成为使得彼此相邻的两个凹槽中的一个更靠近电子器件即阳极电极的形状比位于该外部的另一个凹槽更浅。 然后，绝缘材料沉积在第一槽，第二槽和第三槽中。 然后将半导体衬底的层压体和层压在其上的层切割成切割线。