公开(公告)号：US08319317B2

公开(公告)日：2012-11-27

申请号：US12481292

申请日：2009-06-09

申请人： Katsuyuki Seki ,  Naofumi Tsuchiya ,  Akira Suzuki ,  Kikuo Okada

发明人： Katsuyuki Seki ,  Naofumi Tsuchiya ,  Akira Suzuki ,  Kikuo Okada

IPC分类号： H01L23/58

CPC分类号： H01L21/8222 ,  H01L21/02118 ,  H01L21/312 ,  H01L21/31662 ,  H01L27/0814 ,  H01L2924/10155

摘要： Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N− type semiconductor layer and the thermal oxide film. With the structure described above, an influence of the positive electric charges in the thermal oxide film is weakened and an extension of a depletion layer into the N− type semiconductor layer at the interface with the thermal oxide film is secured.

摘要翻译： 使用便宜的材料来解决传统的台面型半导体器件的问题，其中耐腐蚀性劣化和由与PN结相对应的台面凹槽的内壁上的绝缘膜的厚度减小引起的漏电流的发生 并且提供具有高耐压和高可靠性的台面型半导体器件及其制造方法。 在台面型半导体器件的台面槽的内壁上形成由热氧化膜制成的稳定的保护膜，以覆盖和保护PN结，形成具有负电荷的绝缘膜以填充 用热氧化膜覆盖的台面槽，使得在N-型半导体层和热氧化膜之间的界面处不容易形成电子蓄积层。 利用上述结构，确保了热氧化膜中的正电荷的影响，确保了与热氧化膜的界面处的耗尽层向N型半导体层的延伸。

公开(公告)号：US08227901B2

公开(公告)日：2012-07-24

申请号：US12482674

申请日：2009-06-11

申请人： Katsuyuki Seki ,  Akira Suzuki ,  Keita Odajima ,  Kikuo Okada ,  Koujiro Kameyama

发明人： Katsuyuki Seki ,  Akira Suzuki ,  Keita Odajima ,  Kikuo Okada ,  Koujiro Kameyama

IPC分类号： H01L29/06

CPC分类号： H01L29/861 ,  H01L29/0649 ,  H01L29/6609

摘要： This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment. As a result, the inner wall of the mesa groove corresponding to the PN junction is covered with the second insulation film thick enough to secure a desired withstand voltage and to reduce a leakage current.

摘要翻译： 本发明的目的在于解决台面型半导体器件的问题，这是由于对应于PN结的台面槽的内壁上的第二绝缘膜的厚度减小导致的耐电压劣化和漏电流的发生， 并提供高耐受电压和高可靠性的台面型半导体器件及其制造方法。 在通过干蚀刻形成台面凹槽之后，用包含氢氟酸和硝酸的蚀刻溶液进行湿蚀刻，进一步施加到台面凹槽的侧壁上，以形成由第一绝缘膜上方形成的悬垂 台面凹槽 突出端用作防止形成在台面槽中的第二绝缘膜和围绕突出部分的区域的第一绝缘膜上的第一绝缘膜从底面凹槽的底部流出，这是由于由于 后续热处理。 结果，对应于PN结的台面凹槽的内壁被足够厚的第二绝缘膜覆盖以确保期望的耐受电压并减少漏电流。

公开(公告)号：US20090309194A1

公开(公告)日：2009-12-17

申请号：US12482674

申请日：2009-06-11

申请人： Katsuyuki SEKI ,  Akira Suzuki ,  Keita Odajima ,  Kikuo Okada ,  Koujiro Kameyama

发明人： Katsuyuki SEKI ,  Akira Suzuki ,  Keita Odajima ,  Kikuo Okada ,  Koujiro Kameyama

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L29/861 ,  H01L29/0649 ,  H01L29/6609

摘要： This invention is directed to solving problems with a mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of a second insulation film on an inner wall of a mesa groove corresponding to a PN junction, and offers a mesa type semiconductor device of high withstand voltage and high reliability and its manufacturing method. After the mesa groove is formed by dry-etching, wet-etching with an etching solution including hydrofluoric acid and nitric acid is further applied to a sidewall of the mesa groove to form an overhang made of the first insulation film above an upper portion of the mesa groove. The overhang serves as a barrier to prevent the second insulation film formed in the mesa groove and on the first insulation film around the mesa groove beyond an area of the overhang from flowing toward a bottom of the mesa groove due to an increased fluidity resulting from a subsequent thermal treatment. As a result, the inner wall of the mesa groove corresponding to the PN junction is covered with the second insulation film thick enough to secure a desired withstand voltage and to reduce a leakage current.

摘要翻译： 本发明的目的在于解决台面型半导体器件的问题，这是由于对应于PN结的台面槽的内壁上的第二绝缘膜的厚度减小导致的耐电压劣化和漏电流的发生， 并提供高耐受电压和高可靠性的台面型半导体器件及其制造方法。 在通过干蚀刻形成台面凹槽之后，用包含氢氟酸和硝酸的蚀刻溶液进行湿蚀刻，进一步施加到台面凹槽的侧壁上，以形成由第一绝缘膜上方形成的悬垂 台面凹槽 突出端用作防止形成在台面槽中的第二绝缘膜和围绕突出部分的区域的第一绝缘膜上的第一绝缘膜从底面凹槽的底部流出，这是由于由于 后续热处理。 结果，对应于PN结的台面凹槽的内壁被足够厚的第二绝缘膜覆盖以确保期望的耐受电压并减少漏电流。

公开(公告)号：US07659576B2

公开(公告)日：2010-02-09

申请号：US11933897

申请日：2007-11-01

申请人： Kikuo Okada ,  Kojiro Kameyama

发明人： Kikuo Okada ,  Kojiro Kameyama

IPC分类号： H01L29/78

CPC分类号： H01L29/7395 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66333

摘要： A punch-through type IGBT generally has a thick p++-type collector layer. Therefore, the FWD need be externally attached to the IGBT when the IGBT is used as a switching element in an inverter circuit for driving a motor load, and thus the number of processes and components increases. In the invention, trenches are formed penetrating through a collector layer and reaching a buffer layer. A collector electrode is formed in the trenches, too. With this structure, a current path is formed between an emitter electrode and the collector electrode without through the collector layer and functions as the FWD.

摘要翻译： 穿通型IGBT通常具有厚的p ++型集电极层。 因此，当IGBT用作用于驱动电动机负载的逆变器电路中的开关元件时，FWD需要外部附接到IGBT，因此工艺和部件的数量增加。 在本发明中，形成贯通收集层并到达缓冲层的沟槽。 集电极也形成在沟槽中。 利用这种结构，在发射电极和集电极之间形成电流通路，而不通过集电极层，起到FWD的作用。

公开(公告)号：US20060180836A1

公开(公告)日：2006-08-17

申请号：US11355196

申请日：2006-02-16

申请人： Hiroyasu Ishida ,  Makoto Oikawa ,  Kikuo Okada ,  Shouji Miyahara ,  Naohiro Ochiai ,  Kazunari Kushiyama

发明人： Hiroyasu Ishida ,  Makoto Oikawa ,  Kikuo Okada ,  Shouji Miyahara ,  Naohiro Ochiai ,  Kazunari Kushiyama

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7813

摘要： In the present invention, in a pattern in which gate electrodes are provided in a stripe shape and source regions are provided in a ladder shape, body regions are provided in a stripe shape parallel to the gate electrodes. A first body region is exposed to a surface of a channel layer between first source regions adjacent to the gate electrode, and a second body region is provided below a second source region which connects the first source regions to each other. Thus, avalanche resistance can be improved. Moreover, since a mask for forming the body region is no longer required, there is a margin in accuracy of alignment.

摘要翻译： 在本发明中，在栅电极呈条状而源极区设置为梯状的图案中，以与栅电极平行的条状形成体区。 第一体区域暴露于与栅电极相邻的第一源极区域之间的沟道层的表面，并且第二体区域设置在将第一源极区域彼此连接的第二源极区域的下方。 因此，可以提高雪崩阻力。 此外，由于不再需要用于形成身体区域的掩模，所以对准精度有余量。

公开(公告)号：US06822338B2

公开(公告)日：2004-11-23

申请号：US10374727

申请日：2003-02-27

申请人： Tsutomu Aono ,  Kikuo Okada

发明人： Tsutomu Aono ,  Kikuo Okada

IPC分类号： H01L2348

CPC分类号： H01L24/06 ,  H01L23/49844 ,  H01L23/50 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/056 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48491 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48739 ,  H01L2224/48764 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/49107 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/854 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85464 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012 ,  H01L2924/01033

摘要： A semiconductor device includes a power supply semiconductor chip that has a current passing electrode. A conductive plate is disposed on the current electrode, and a conductive wire that is used for an external connection of the device is fixed on the conductive plate, but not directly on the current passing electrode. The conductive plate may serve as a shock absorber during wire bonding procedure, and may contact more than one current passing electrodes so that the number of wire bonding procedures is reduced in manufacturing the device.

摘要翻译： 半导体器件包括具有电流通过电极的电源半导体芯片。 导电板设置在电流电极上，并且用于器件的外部连接的导线固定在导电板上，而不是直接放置在通过电极上。 在引线接合过程中，导电板可以用作减震器，并且可以接触多于一个电流通过的电极，使得在制造器件时减少引线接合程序的数量。

公开(公告)号：US5443700A

公开(公告)日：1995-08-22

申请号：US283175

申请日：1994-08-03

申请人： Yasuo Hirose ,  Kikuo Okada

发明人： Yasuo Hirose ,  Kikuo Okada

IPC分类号： C02F1/28 ,  C02F1/46 ,  C02F1/461 ,  C02F1/58

CPC分类号： C02F1/46114 ,  C02F1/283 ,  C02F2101/303

摘要： A method for treating waster water containing oil composed of esters, which makes reactivation of spent adsorbent possible or unnecessary, and facilitates treatment of waste adsorbent. In order to realize the above method, oil composed of esters is adsorbed into an electroconductive adsorbent from the waste water, and is converted to water soluble materials by electrolytic hydrolysis using the adsorbent as a part of cathode for separating from and reactivating the adsorbent, or adsorbing step and reactivating step are performed concurrently. In accordance with the present invention, reactivation of spent adsorbent becomes possible and an amount of generated waste decreases remarkably, and generated waste adsorbent hitherto can be readily incinerated because of eliminating adsorbed oil. Secondary waste is not generated because no chemicals are used other than electric power.

摘要翻译： 一种用于处理由酯组成的含水油的方法，其使残留吸附剂可再生或不需要再次活化，并且便于处理废吸附剂。 为了实现上述方法，将由酯组成的油从废水吸附到导电吸附剂中，并通过电解水解将其转化为水溶性材料，使用吸附剂作为阴极的一部分，用于分离和再活化吸附剂，或 吸附步骤和再次活化步骤同时进行。 根据本发明，废吸附剂的再活化成为可能，并且所产生的废弃物的量显着降低，并且迄今为止生成的废吸附剂可以容易地被焚烧，因为消除吸附的油。 不会产生二次废物，因为除了电力之外没有使用任何化学物质。

公开(公告)号：US20090315175A1

公开(公告)日：2009-12-24

申请号：US12307228

申请日：2008-04-04

申请人： Kikuo Okada ,  Kojiro Kameyama ,  Takahiro Oikawa

发明人： Kikuo Okada ,  Kojiro Kameyama ,  Takahiro Oikawa

IPC分类号： H01L23/498 ,  H01B5/00

CPC分类号： H01L23/49562 ,  H01L23/4952 ,  H01L23/49524 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/91 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7809 ,  H01L29/7813 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/371 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099

摘要： In a power MOS transistor, for example, a source electrode is formed so as to be commonly connected to a plurality of source regions formed on the front surface. Thus, a current density varies based on in-plane resistance of the source electrode, thereby providing the necessity of increasing the number of wires connecting the sources and a lead. In the invention, an electrode structure includes a copper plating layer 10e formed on a pad electrode 10a by an electrolytic plating method, and a nickel plating layer 10f and a gold plating layer formed so as to cover the upper and side surfaces of the copper plating layer 10e by an electroless plating method.

摘要翻译： 在功率MOS晶体管中，例如，源极电极形成为与形成在前表面上的多个源极区域共同连接。 因此，电流密度基于源电极的面内电阻而变化，由此提供增加连接源极和引线的导线数量的必要性。 在本发明中，电极结构包括通过电解电镀法形成在焊盘电极10a上的镀铜层10e，以及形成为覆盖铜镀层的上表面和侧表面的镀镍层10f和镀金层 层10e通过化学镀方法。

公开(公告)号：US20080038880A1

公开(公告)日：2008-02-14

申请号：US11882883

申请日：2007-08-06

申请人： Kikuo Okada ,  Tetsuya Okada

发明人： Kikuo Okada ,  Tetsuya Okada

IPC分类号： H01L21/332

CPC分类号： H01L29/7395 ,  H01L29/66333

摘要： There is the need to grind a semiconductor substrate from its back surface in order to thin a drift region for forming the NPT type IGBT. A collector region is then formed on the back surface of the semiconductor substrate by performing ion-implantation, a heat treatment and the like to the back surface of the semiconductor substrate of which the strength is weakened. This causes problems of warping the semiconductor substrate and the like. In a method of manufacturing a semiconductor device of the invention, the thickness of a drift region is previously adjusted by the thickness of an epitaxial layer. A collector region is then formed only by grinding a semiconductor substrate. In particular, using a semiconductor substrate containing a low concentration of impurity provides preferable characteristics for a high-speed switching element with a short turn-off time even when the collector region is thick.

摘要翻译： 为了使用于形成NPT型IGBT的漂移区域变薄，需要从其背面研磨半导体衬底。 然后，通过对半导体基板的强度弱化的背面进行离子注入，热处理等，在半导体基板的背面形成集电极区域。 这导致了半导体衬底翘曲等问题。 在制造本发明的半导体器件的方法中，预先通过外延层的厚度调整漂移区的厚度。 然后仅通过研磨半导体衬底形成集电极区域。 特别是使用含有低浓度杂质的半导体衬底，即使在集电极区域较厚的情况下也能够实现具有短关断时间的高速开关元件的优选特性。

公开(公告)号：US06841421B2

公开(公告)日：2005-01-11

申请号：US10374728

申请日：2003-02-27

申请人： Tsutomu Aono ,  Kikuo Okada

发明人： Tsutomu Aono ,  Kikuo Okada

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L27/10 ,  H01L21/44

CPC分类号： H01L27/10 ,  H01L23/5222 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45601 ,  H01L2224/48472 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45644 ,  H01L2224/45639 ,  H01L2224/45664

摘要： A semiconductor device includes a power supply semiconductor chip that has a plurality of current passing electrodes. Conductive plates are disposed on the current electrodes, and conductive wires used for an external connection of the device are fixed on the conductive plates, but not directly on the current passing electrode. A large plate is first fixed on the semiconductor chip, and then the back surface of the large plate is removed to form the individual conductive plates. Because the conductive wires are soldered onto the conductive plates, the semiconductor chip does not receive impact of wire bonding. Even when the conductive wires are wire bonded to the conductive plates, the plates may serve as shock absorbers during wire bonding procedure to reduce the impact of the wire bonding.

摘要翻译： 半导体器件包括具有多个电流通过电极的电源半导体芯片。 导电板设置在电流电极上，用于器件外部连接的导线固定在导电板上，而不是直接穿过电流通过的电极。 首先将大的板固定在半导体芯片上，然后去除大板的后表面以形成各个导电板。 由于导线被焊接到导电板上，所以半导体芯片不会受到引线接合的冲击。 即使当导线被导线接合到导电板上时，板也可以在引线接合过程中用作减震器，以减少引线接合的冲击。