公开(公告)号：US20100194618A1

公开(公告)日：2010-08-05

申请号：US12597881

申请日：2009-02-10

申请人： Hiroki Mouri ,  Kouichi Nagano

发明人： Hiroki Mouri ,  Kouichi Nagano

IPC分类号： H03M1/36

CPC分类号： H03M1/186 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10425 ,  G11B2220/2541 ,  G11B2220/2562 ,  H03M1/365

摘要： A plurality of comparators (CMP1, CMP2, . . . ) respectively correspond to a plurality of reference voltages (V1, V2, . . . ), and each compares a reference voltage corresponding to the comparator-with a signal level of an analog signal (Sin). An encoder (102) generates a digital signal (De) corresponding to the analog signal (Sin) based on outputs (S1, S2, . . . ) of the plurality of comparators. A pattern detection circuit (103) detects that a temporal change of an output (S3) of a first comparator matches a predetermined first particular pattern. A control circuit (104) corrects a digital value of the digital signal (De) in response to detection by the pattern detection circuit. The temporal change of the output (S3) of the first comparator becomes the first particular pattern when an amplitude of the analog signal (Sin) is smaller than a predetermined amplitude.

摘要翻译： 多个比较器（CMP1，CMP2 ...）分别对应于多个参考电压（V1，V2 ...），并且每个比较器将对应于比较器的参考电压与模拟信号的信号电平进行比较 （罪）。 编码器（102）基于多个比较器的输出（S1，S2，...）生成与模拟信号（Sin）相对应的数字信号（De）。 模式检测电路（103）检测第一比较器的输出（S3）的时间变化与预定的第一特定模式匹配。 响应于图案检测电路的检测，控制电路（104）校正数字信号（De）的数字值。 当模拟信号（Sin）的幅度小于预定幅度时，第一比较器的输出（S3）的时间变化变为第一特定模式。

公开(公告)号：US20080101176A1

公开(公告)日：2008-05-01

申请号：US11794228

申请日：2005-10-20

申请人： Hiroki Mouri ,  Hiroyuki Nakahira ,  Kouichi Nagano

发明人： Hiroki Mouri ,  Hiroyuki Nakahira ,  Kouichi Nagano

IPC分类号： G11B7/00

CPC分类号： G11B7/00456 ,  G11B7/0045 ,  G11B7/126 ,  G11B20/10009 ,  G11B20/10222 ,  G11B20/10425 ,  G11B20/1403 ,  G11B2220/2537 ,  H03K5/135

摘要： There has been an issue that the operation of a semiconductor circuit performing edge timing control cannot follow up in the multipulse generation process where high multiplication of speed progresses every year. A light strategy drive comprises a control register (22) storing timing edge information for generating the edge of a recording waveform signal, a PLL (23) generating a clock for generating the edge of a recording waveform signal, and a timing control circuit (24) for receiving timing edge information corresponding to the recording waveform signal from the control register (22) to output timing edge information having a predetermined amount of delay in parallel and compounding the edges based on the timing edge information outputted in parallel. Timing edge can be controlled with high precision even at the time of high speed operation, and a high precision multipulse can be generated.

摘要翻译： 存在这样的问题，即，进行边缘定时控制的半导体电路的动作不能随着速度的高乘法每年进行的多脉冲生成处理而跟随。 光策略驱动器包括存储用于产生记录波形信号的边缘的定时边缘信息的控制寄存器（22），产生用于产生记录波形信号的边缘的时钟的PLL（23）和定时控制电路（24 ），用于接收与来自控制寄存器（22）的记录波形信号相对应的定时边缘信息，以基于并行输出的定时边缘信息并行输出具有预定延迟量的定时边缘信息并使边缘复合。 即使在高速运转时，也可以高精度地控制定时边缘，能够产生高精度的多脉冲。

公开(公告)号：US07898451B2

公开(公告)日：2011-03-01

申请号：US12597881

申请日：2009-02-10

申请人： Hiroki Mouri ,  Kouichi Nagano

发明人： Hiroki Mouri ,  Kouichi Nagano

IPC分类号： H03M1/36

CPC分类号： H03M1/186 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10425 ,  G11B2220/2541 ,  G11B2220/2562 ,  H03M1/365

摘要： A plurality of comparators (CMP1, CMP2, . . . ) respectively correspond to a plurality of reference voltages (V1, V2, . . . ), and each compares a reference voltage corresponding to the comparator with a signal level of an analog signal (Sin). An encoder (102) generates a digital signal (De) corresponding to the analog signal (Sin) based on outputs (S1, S2, . . . ) of the plurality of comparators. A pattern detection circuit (103) detects that a temporal change of an output (S3) of a first comparator matches a predetermined first particular pattern. A control circuit (104) corrects a digital value of the digital signal (De) in response to detection by the pattern detection circuit. The temporal change of the output (S3) of the first comparator becomes the first particular pattern when an amplitude of the analog signal (Sin) is smaller than a predetermined amplitude.

摘要翻译： 多个比较器（CMP1，CMP2 ...）分别对应于多个参考电压（V1，V2 ...），并且每个比较器将对应于比较器的参考电压与模拟信号的信号电平 罪）。 编码器（102）基于多个比较器的输出（S1，S2，...）生成与模拟信号（Sin）相对应的数字信号（De）。 模式检测电路（103）检测第一比较器的输出（S3）的时间变化与预定的第一特定模式匹配。 响应于图案检测电路的检测，控制电路（104）校正数字信号（De）的数字值。 当模拟信号（Sin）的幅度小于预定幅度时，第一比较器的输出（S3）的时间变化变为第一特定模式。

公开(公告)号：US07065029B2

公开(公告)日：2006-06-20

申请号：US10170581

申请日：2002-06-14

申请人： Hiroki Mouri ,  Kouichi Nagano ,  Akira Yamamoto

发明人： Hiroki Mouri ,  Kouichi Nagano ,  Akira Yamamoto

IPC分类号： G11B7/00

CPC分类号： G11B20/10166 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10055 ,  G11B20/10212

摘要： A waveform equalizer, which has a partial response characteristic represented in the form of PR (a, b, c, b, a) which is a quaternary transfer function characteristic, is made up an analog filter, an ADC (analog/digital converter), and an FIR filter, for providing matching with the frequency characteristic of a read back waveform read from a recording medium. Such signal processor characteristic approximation to the regenerative signal characteristic makes it possible to easily achieve equalization without particularly emphasizing the regenerative signal, thereby achieving a reduced circuit scale.

公开(公告)号：US20090228538A1

公开(公告)日：2009-09-10

申请号：US12092938

申请日：2006-10-24

申请人： Kouichi Nagano ,  Hiroyuki Nakahira

发明人： Kouichi Nagano ,  Hiroyuki Nakahira

IPC分类号： G06F7/52 ,  G06F7/00

CPC分类号： G06F7/533

摘要： Conventional multi-input multiplication and addition circuit having fixed multipliers has problems in that when the number of inputs increases, the number of partial product generator circuits would increase, and also the number of stages of the addition blocks would increase.In order to solve the above-described problems, it is constructed such that there are provided a multi-input encoder (11) which comprises a plurality of encoder parts (11a) each of which accomplishes a function corresponding to generation of a partial product in multiplication, and which also has a plurality of outputs which correspond to the multi-bit output of the respective encoder parts, and a multi-input adder circuit (12) which adds the plural outputs from the multi-input encoder (11).

摘要翻译： 具有固定乘法器的常规多输入乘法和加法电路存在的问题在于，当输入数量增加时，部分乘积发生器电路的数量将增加，并且加法块的级数也将增加。 为了解决上述问题，构成为提供一种多输入编码器（11），该多输入编码器（11）包括多个编码器部分（11a），每个编码器部分完成与产生部分积的功能相对应的功能 并且还具有对应于各个编码器部分的多位输出的多个输出，以及将来自多输入编码器（11）的多个输出相加的多输入加法器电路（12）。

公开(公告)号：US07187729B2

公开(公告)日：2007-03-06

申请号：US10339321

申请日：2003-01-10

申请人： Kouichi Nagano

发明人： Kouichi Nagano

IPC分类号： H03D1/00

CPC分类号： H03M13/6331 ,  H03M13/41 ,  H03M13/43 ,  H03M13/6502

摘要： A path storing circuit has path holding parts at a plurality of stages storing a survivor path and corresponding to times. A majority decision circuit receives output values of three delay circuits including the top and bottom delay circuits each receiving a selected output of a selector out of six delay circuits in the path holding part at the final stage and makes a decision by a majority.

摘要翻译： 路径存储电路具有存储幸存路径并对应于时间的多个级的路径保持部。 多数决定电路接收三个延迟电路的输出值，包括顶延迟电路和下延迟电路，每个延迟电路在最终阶段的路径保持部分中的六个延迟电路中接收选择器的选定输出，并且通过多数决定。

公开(公告)号：US20090030963A1

公开(公告)日：2009-01-29

申请号：US12279459

申请日：2007-02-08

申请人： Kouichi Nagano

发明人： Kouichi Nagano

IPC分类号： G06F7/38 ,  G06F7/503

CPC分类号： G06F7/5324 ,  G06F7/5338

摘要： The conventional two's complement multiplier which is constituted by a Booth encoder, a partial production generation circuit, and an adder has a problem that the circuit scale would be increased because a bit extension is performed when the multiplier is adapted to an unsigned multiplication.A multiplication circuit of the present invention is provided with a first Booth encoder (1) for encoding lower-order several bits of a multiplier according to first rules of encoding using a Booth algorithm, and a second Booth encoder (5) for encoding most-significant several bits of the multiplier according to second rules of encoding using a Booth algorithm, which are different from the first rules of encoding, and thereby the most-significant several bits of the multiplier are encoded using the Booth algorithm which is different from that for the lower-order several bits.

摘要翻译： 由布斯编码器，部分产生电路和加法器构成的常规二进制补码乘法器具有由于当乘法器适应于无符号乘法时执行比特扩展，电路规模将增加的问题。 本发明的乘法电路具有：第一布斯编码器（1），用于根据使用布斯算法的编码的第一规则对乘法器的低位数位进行编码，第二布斯编码器（5） 根据与第一编码规则不同的Booth算法，根据使用第二规则编码的乘法器的有效数位，从而乘法器的最重要的几个比特用Booth算法进行编码，该Booth算法与 低位几位。

公开(公告)号：US20070297307A1

公开(公告)日：2007-12-27

申请号：US11665718

申请日：2005-09-12

申请人： Kouichi Nagano

发明人： Kouichi Nagano

IPC分类号： G11B7/0045 ,  G11B7/125

CPC分类号： G11B7/00456 ,  G11B20/10009 ,  G11B20/10212 ,  G11B20/10222 ,  G11B2220/2537

摘要： A write correction circuit (100) includes, in its input stage, a pulse modification circuit (11) for removing patterns (sections) included in a write pulse signal (s1), which patterns have lengths outside a range that is previously determined as a section length of the write pulse signal, and outputting a modified pulse signal (s1) that is obtained by modifying the waveform of the write pulse signal, and write correction is performed to the modified pulse signal (s11) that is obtained in the pulse modification circuit (11). Thereby, highly precise write correction can be performed to the write pulse signal (s1) inputted to the write correction circuit (100).

摘要翻译： 写入校正电路（100）在其输入级包括用于去除包括在写入脉冲信号（s 1）中的图形（部分）的脉冲修改电路（11），该图形具有超出预先确定为 写入脉冲信号的截面长度，并且输出通过修改写入脉冲信号的波形获得的修改的脉冲信号（s 1），并且对修改的脉冲信号（s 11）进行写入校正，该修改脉冲信号 脉冲修正电路（11）。 因此，可以对输入到写入校正电路（100）的写入脉冲信号（s 1）执行高精度的写入校正。

公开(公告)号：US07142382B2

公开(公告)日：2006-11-28

申请号：US10944917

申请日：2004-09-21

申请人： Kouichi Nagano

发明人： Kouichi Nagano

IPC分类号： G11B5/09 ,  G11B27/10

CPC分类号： H03C3/02 ,  G11B7/0053

摘要： A phase adjustment circuit includes: a carrier-wave-delay adjusting circuit for delaying an input carrier wave and outputting the delayed carrier wave, in accordance with phase information; and a phase-difference detecting/adjusting circuit for detecting a phase difference between an input signal and the delayed carrier wave, outputting, as the phase information, a value according to the detected phase difference, adjusting the delayed carrier wave such that the delayed carrier wave has a phase substantially coincident with a phase of the input signal, and outputting the resultant carrier wave as a phase-adjusted carrier wave. In a steady state, the phase-difference detecting/adjusting circuit outputs, as the phase information, a value indicating the presence of a phase difference.

摘要翻译： 相位调整电路包括：载波延迟调整电路，用于根据相位信息延迟输入载波并输出延迟的载波; 以及相位差检测/调整电路，用于检测输入信号和延迟的载波之间的相位差，输出根据检测的相位差的值作为相位信息，调整延迟的载波，使得延迟的载波 波具有与输入信号的相位基本一致的相位，并将所得到的载波作为相位调整载波输出。 在稳定状态下，相位差检测/调整电路输出表示存在相位差的值作为相位信息。

公开(公告)号：US08223902B2

公开(公告)日：2012-07-17

申请号：US13206226

申请日：2011-08-09

申请人： Fumiaki Senoue ,  Kouichi Nagano

发明人： Fumiaki Senoue ,  Kouichi Nagano

IPC分类号： H03D1/04 ,  H04B1/10

CPC分类号： H04B1/30 ,  H03D3/009 ,  H04L27/3863

摘要： An analog complex filter combines an in-phase signal and a quadrature signal to output first and second analog signals. An analog-to-digital converter converts the first and second analog signals into first and second digital signals. A digital complex filter attenuates components corresponding to the quadrature signal and the in-phase signal of the first and second digital signals, respectively. A digital bandwidth limited filter allows a target component and an image component contained in the digital complex signal composed of the first and second digital signals from the digital complex filter to pass therethrough, and attenuates an adjacent interference component. An IQ imbalance correction circuit corrects a quadrature error and an amplitude error between the first and second digital signals from the digital band-pass filter.

摘要翻译： 模拟复合滤波器将同相信号和正交信号组合以输出第一和第二模拟信号。 模数转换器将第一和第二模拟信号转换成第一和第二数字信号。 数字复合滤波器分别衰减对应于第一和第二数字信号的正交信号和同相信号的分量。 数字带宽限制滤波器允许包含在由数字复合滤波器的第一和第二数字信号组成的数字复合信号中的目标分量和图像分量通过，并衰减相邻的干扰分量。 IQ不平衡校正电路校正来自数字带通滤波器的第一和第二数字信号之间的正交误差和振幅误差。