公开(公告)号：US08008734B2

公开(公告)日：2011-08-30

申请号：US11972932

申请日：2008-01-11

申请人： Hiroki Wakimoto ,  Masahito Otsuki ,  Takashi Shiigi

发明人： Hiroki Wakimoto ,  Masahito Otsuki ,  Takashi Shiigi

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66734 ,  H01L29/7813

摘要： A power semiconductor device is provided having a field plate that employs a thick metal film in an edge termination structure and which permits edge termination structure width reduction even with large side etching or etching variation, which exhibits superior long-term forward blocking voltage capability reliability, and which allows minimal forward blocking voltage capability variation. The edge termination structure has multiple ring-like p-type guard rings, a first insulating film covering the guard rings, and ring-like field plates, provided via the first insulating film atop the guard rings. The field plates have a polysilicon film and a thicker metal film. The polysilicon film is provided on a first guard ring via first insulating film, and a dual field plate made of the polysilicon film and metal film is provided on a second guard ring. The dual field plate is stacked via a second insulating film. The first and second guard rings alternate.

摘要翻译： 提供了一种功率半导体器件，其具有采用边缘端接结构中的厚金属膜的场板，即使具有优异的长期正向阻断电压能力可靠性的大的侧蚀刻或蚀刻变化也允许边缘终端结构宽度减小， 并且其允许最小的正向阻断电压能力变化。 边缘端接结构具有多个环状p型保护环，覆盖保护环的第一绝缘膜和通过护罩顶部上的第一绝缘膜提供的环状场板。 场板具有多晶硅膜和较厚的金属膜。 多晶硅膜通过第一绝缘膜设置在第一保护环上，并且由多晶硅膜和金属膜制成的双场板设置在第二保护环上。 双场板通过第二绝缘膜堆叠。 第一和第二保卫环交替出现。

公开(公告)号：US07462911B2

公开(公告)日：2008-12-09

申请号：US11561652

申请日：2006-11-20

申请人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

发明人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0696 ,  H01L29/7397

摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.

摘要翻译： 公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。 它包括通过沟槽分成不同p型基极区的p型基极层。 仅在一些p型基区中形成N型源极区。 在沟槽IGBT的有源区域中有一个栅极流道。 形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。 与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关，由式25 <= {N1 /（N1 + N2）}×100 <= 75。

公开(公告)号：US06737705B2

公开(公告)日：2004-05-18

申请号：US09843251

申请日：2001-04-26

申请人： Seiji Momota ,  Yuichi Onozawa ,  Masahito Otsuki ,  Hiroki Wakimoto

发明人： Seiji Momota ,  Yuichi Onozawa ,  Masahito Otsuki ,  Hiroki Wakimoto

IPC分类号： H01L29745

CPC分类号： H01L29/7397 ,  H01L29/1095 ,  H01L29/407

摘要： A trench-type IGBT includes a silicon substrate, a lightly doped n-type drift layer on the silicon substrate, and a p-type base layer on the n-type drift layer. The p-type base layer is doped more heavily than the n-type drift layer, and is formed of first regions and second regions. N+-type source regions are formed selectively in the surface portions of the first regions of p-type base layer. Trenches are dug from the surfaces of n+-type source regions down to the n-type drift layer through the p-type base layer. A gate oxide film covers the inner surface of each trench. Gate electrodes are provided in the trenches, wherein the gate electrodes face the p-type base layer via respective gate oxide films. An emitter electrode is in direct contact with the first regions of p-type base layer and n+-type source regions. A collector electrode is provided on the back surface of silicon substrate. The ratio of the width of the first regions to the width of the second regions of p-type base layer is from 1:2 to 1:7. The device facilitates in reducing the total losses by reducing the switching loss while suppressing the on-voltage thereof as low as the on-voltage of the IEGT.

摘要翻译： 沟槽型IGBT包括硅衬底，硅衬底上的轻掺杂n型漂移层和n型漂移层上的p型基极层。 p型基极层比n型漂移层掺杂更多，由第一区域和第二区域形成。 在p型基底层的第一区域的表面部分中选择性地形成N +型源极区域。 沟槽从n +型源区的表面通过p型基底层向下到达n型漂移层。 栅极氧化膜覆盖每个沟槽的内表面。 栅极设置在沟槽中，其中栅电极经由相应的栅氧化膜面对p型基极层。 发射极电极与p型基极层和n +型源极区域的第一区域直接接触。 集电极设置在硅衬底的背面上。 第一区域的宽度与p型基底层的第二区域的宽度的比例为1:2至1:7。 该器件通过降低开关损耗同时将其导通电压抑制得低至IEGT的导通电压，从而有助于降低总损耗。

公开(公告)号：US07737490B2

公开(公告)日：2010-06-15

申请号：US11741015

申请日：2007-04-27

申请人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

发明人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

IPC分类号： H01L29/76

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

摘要翻译： 提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且 选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。 这使得器件能够实现低导通电阻和增强的关断能力。

公开(公告)号：US07151297B2

公开(公告)日：2006-12-19

申请号：US10993146

申请日：2004-11-19

申请人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

发明人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0696 ,  H01L29/7397

摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.

摘要翻译： 公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。 它包括通过沟槽分成不同p型基极区的p型基极层。 仅在一些p型基区中形成N型源极区。 在沟槽IGBT的有源区域中有一个栅极流道。 形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。 与发射极电气电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关联，通过表达式25 <= {N1 /（N1 + N2x100 <= 75。

公开(公告)号：US20050151187A1

公开(公告)日：2005-07-14

申请号：US10993146

申请日：2004-11-19

申请人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

发明人： Hiroki Wakimoto ,  Seiji Momota ,  Masahito Otsuki

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/739 ,  H01L29/76

CPC分类号： H01L29/0696 ,  H01L29/7397

摘要： A trench IGBT is disclosed which meets the specifications for turn-on losses and radiation noise. It includes a p-type base layer divided into different p-type base regions by trenches. N-type source regions are formed in only some of the p-type base regions. There is a gate runner in the active region of the trench IGBT. Contact holes formed in the vicinities of the terminal ends of the trenches and on both sides of the gate runner electrically connect some of the p-type base regions that do not include source regions to an emitter electrode. The number N1 of p-type base regions that are connected electrically to the emitter electrode and the number N2 of p-type base regions that are insulated from the emitter electrode are related with each other by the expression 25≦{N1/(N1+N2)}×100≦75.

摘要翻译： 公开了一种满足导通损耗和辐射噪声规范的沟槽IGBT。 它包括通过沟槽分成不同p型基极区的p型基极层。 仅在一些p型基区中形成N型源极区。 在沟槽IGBT的有源区域中存在栅极流道。 形成在沟槽的末端附近并且栅极流道两侧的接触孔将不包括源极区域的一些p型基极区域电连接到发射极电极。 与发射电极电连接的p型基极区域的数量N1和与发射极电极绝缘的p型基极区域的数量N2彼此相关联，表达式25 <= {N1 /（N1 + N2x100 <= 75。

公开(公告)号：US20070252195A1

公开(公告)日：2007-11-01

申请号：US11741015

申请日：2007-04-27

申请人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

发明人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

IPC分类号： H01L31/00

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

摘要翻译： 提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且 选择性地形成在p型沟道区域的表面上的n + + +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。 这使得器件能够实现低导通电阻和增强的关断能力。

公开(公告)号：US08242556B2

公开(公告)日：2012-08-14

申请号：US12767356

申请日：2010-04-26

申请人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

发明人： Koh Yoshikawa ,  Hiroki Wakimoto ,  Masahito Otsuki

IPC分类号： H01L29/76

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/66348

摘要： A vertical and trench type insulated gate MOS semiconductor device is provided in which the surfaces of p-type channel regions and the surfaces of portions of an n-type semiconductor substrate alternate in the longitudinal direction of the trench between the trenches arranged in parallel, and an n+-type emitter region selectively formed on the surface of the p-type channel region is wide by the side of the trench and becomes narrow toward the center point between the trenches. This enables the device to achieve low on-resistance and enhanced turn-off capability.

摘要翻译： 提供一种垂直和沟槽型绝缘栅极MOS半导体器件，其中p型沟道区域的表面和n型半导体衬底的部分表面在沟槽纵向方向上交替排列成平行布置，并且 选择性地形成在p型沟道区域的表面上的n +型发射极区域在沟槽侧面较宽，并且朝向沟槽之间的中心点变窄。 这使得器件能够实现低导通电阻和增强的关断能力。

公开(公告)号：US5894139A

公开(公告)日：1999-04-13

申请号：US864290

申请日：1997-05-28

申请人： Masahito Otsuki ,  Ryu Saito ,  Yasuhiko Onishi

发明人： Masahito Otsuki ,  Ryu Saito ,  Yasuhiko Onishi

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7395 ,  H01L29/0696 ,  H01L29/1095

摘要： A semiconductor device is provided which includes a first-conductivity-type collector layer having a rear surface on which a collector electrode is formed, a second-conductivity-type buffer layer laminated on the collector layer, a second-conductivity-type conductivity modulation layer formed on the buffer layer, a first-conductivity-type emitter layer formed as a well in a surface of the conductivity modulation layer, a second-conductivity-type source region formed in a surface of a well edge portion of the emitter layer, a gate electrode formed through a gate insulating film to overlap the source region and the conductivity modulation layer, and an emitter electrode that is in ohmic contact with both the emitter layer and the source region. In the present device, the second-conductivity-type source region includes a second-conductivity-type source region formed in the well edge of the emitter layer, and a second-conductivity-type source contact region formed adjacent to the source region and held in ohmic contact with the emitter electrode. This source contact region has a higher impurity concentration than the source region.

摘要翻译： 提供了一种半导体器件，其包括具有形成有集电极的后表面的第一导电型集电体层，层叠在集电极层上的第二导电型缓冲层，第二导电型导电性调制层 形成在缓冲层上的第一导电型发射极层，形成在导电性调制层的表面中的第一导电型发射极层，形成在发射极层的阱边缘部分的表面中的第二导电型源极区域， 栅极电极通过栅极绝缘膜形成以与源极区域和导电性调制层重叠，以及与发射极层和源极区域欧姆接触的发射极。 在本装置中，第二导电型源极区域包括形成在发射极层的阱边缘中的第二导电型源极区域和与源极区域相邻形成并保持的第二导电型源极接触区域 与发射极电极欧姆接触。 该源极接触区域具有比源极区域更高的杂质浓度。

公开(公告)号：US5559347A

公开(公告)日：1996-09-24

申请号：US397418

申请日：1995-03-01

申请人： Tomoyuki Yamazaki ,  Masahito Otsuki

发明人： Tomoyuki Yamazaki ,  Masahito Otsuki

IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/04 ,  H01L29/739 ,  H01L29/74 ,  H01L29/76

CPC分类号： H01L29/7395 ,  H01L27/0248

摘要： An insulated gate-type bipolar transistor with an overcurrent limiting function that is capable of keeping the ratio of a main current to a detection current constant even under different operating conditions, and capable of suppressing the voltage dependence of the limited-current value to perform stable overcurrent protection. P-wells are formed so that they are incorporated between main cell IGBTs as sensing cells for current detection on part of the semiconductor substrate on which a large number of main cells are formed integratedly, and current-detecting emitter electrodes connected to the P-wells are connected to an overcurrent-protection circuit and separated from the main emitter electrodes connected to the main IGBT cells. Given such a configuration, the overcurrent flowing into the main cells during a load short circuit in an inverter device is detected as a hole current from the P-wells with a high accuracy of keeping the current ratio to the current in the main cells constant, and moreover, stable overcurrent protection is performed keeping the limited current values suppressed below the short-circuit withstand capability without dependence on the power supply voltage.

摘要翻译： 具有过电流限制功能的绝缘栅型双极晶体管，即使在不同的工作条件下也能够使主电流与检测电流的比例保持恒定，并且能够抑制有限电流值的电压依赖性而稳定 过电流保护。 形成P阱，使得它们被结合在主电池IGBT之间作为在其上集成有大量主电池的部分半导体衬底上进行电流检测的感测单元，以及连接到P阱的电流检测发射极 连接到过电流保护电路，并与连接到主IGBT单元的主发射极分离。 给出这样的结构，在逆变器装置中的负载短路期间流入主电池的过电流以与主电池中的电流恒定的高精度从P阱检测为空穴电流， 而且，在不依赖于电源电压的情况下，将受限电流值保持在短路耐受能力以下，进行稳定的过电流保护。