公开(公告)号：US4300234A

公开(公告)日：1981-11-10

申请号：US83527

申请日：1979-10-10

申请人： Hiromi Maruyama ,  Takashi Tokuno ,  Masao Shimizu ,  Kohji Ishikawa ,  Naoaki Narumi ,  Osamu Ohguchi

发明人： Hiromi Maruyama ,  Takashi Tokuno ,  Masao Shimizu ,  Kohji Ishikawa ,  Naoaki Narumi ,  Osamu Ohguchi

IPC分类号： G06F11/22 ,  G01R31/3181 ,  G01R31/3183 ,  G11C8/00 ,  G11C29/10 ,  G11C29/56 ,  G01R31/28

CPC分类号： G11C29/56 ,  G01R31/31813

摘要： An address pattern generator for use in a test pattern generator for generating various patterns for testing semiconductor memories. A plurality of fixed registers for storing an initial value at the start of a test, a boundary value and an operand indicating the amount of change of an address are provided in common to at least two address operating circuits. The address operating circuits are each capable of taking therein the content of a desired one of the fixed registers. At least two output registers are provided, which are each capable of taking therein the operation result of a desired one of the address operating circuit. The contents of these output registers are supplied as addresses to a memory under test.

摘要翻译： 一种用于测试图形发生器的地址模式发生器，用于产生用于测试半导体存储器的各种模式。 多个固定寄存器用于在测试开始时存储初始值，边界值和指示地址变化量的操作数被共同地提供给至少两个地址操作电路。 地址操作电路各自能够在其中接收期望的一个固定寄存器的内容。 提供至少两个输出寄存器，每个输出寄存器能够在其中接收所需地址操作电路的操作结果。 这些输出寄存器的内容作为地址提供给被测内存。

公开(公告)号：US4293950A

公开(公告)日：1981-10-06

申请号：US26246

申请日：1979-04-02

申请人： Masao Shimizu ,  Takashi Tokuno ,  Kohji Ishikawa ,  Naoaki Narumi ,  Osamu Ohguchi

发明人： Masao Shimizu ,  Takashi Tokuno ,  Kohji Ishikawa ,  Naoaki Narumi ,  Osamu Ohguchi

IPC分类号： G01R31/3181 ,  G01R31/319 ,  G11C29/10 ,  G11C29/56 ,  G06F11/00 ,  G01R31/28

CPC分类号： G01R31/31921 ,  G11C29/10 ,  G11C29/56 ,  G01R31/31813

摘要： A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the address pattern, by which the data pattern may be inverted and then outputted.

摘要翻译： 读取描述要生成的测试图案的微程​​序的测试图形生成装置，用于解释和执行，地址和数据模式通过算术运算产生，并且产生存储器控制信号，地址和数据模式以及存储器控制信号 被应用于被测记忆体。 地址模式被提供给区域反转控制信号产生部分，以产生对应于地址模式的反转控制信号，由此可以将数据模式反转并输出。

公开(公告)号：US4310802A

公开(公告)日：1982-01-12

申请号：US69348

申请日：1979-08-24

申请人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Takashi Tokuno

发明人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Takashi Tokuno

IPC分类号： G06F11/22 ,  G01R31/3183 ,  G01R31/319 ,  G06F1/06 ,  H03K5/135 ,  H03K5/156 ,  H03K5/22

CPC分类号： G01R31/31922 ,  H03K5/156 ,  G01R31/31928

摘要： Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.

摘要翻译： 输入逻辑数据由每个时隙的数据分割电路顺序划分成n个数据列，每个数据块具有n个时隙长度。 可以任意定时的时钟信号由时钟分频电路划分成n个时钟信号，这些时钟信号在相位上分离一个时隙并且以n个时隙的周期发生。 在逻辑电路中，划分的时钟信号由对应的分割数据串进行控制，并且受控时钟信号由复用电路进行时间复用，从而获得输入逻辑数据已被时钟信号定时的输出数据 。