公开(公告)号：US4270116A

公开(公告)日：1981-05-26

申请号：US69347

申请日：1979-08-24

Applicant: Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Masao Shimizu ,  Toshiaki Wakita

Inventor： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Masao Shimizu ,  Toshiaki Wakita

IPC: G01R31/28 ,  G06F7/02 ,  G06F7/04 ,  G06F11/22

CPC classification number: G06F7/02

Abstract: Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.

Abstract translation: 参考逻辑数据由每个时隙的数据分割电路在空间上划分，并且分割的数据被转换成数据，每个数据具有连续的有效周期。 通过比较器比较分割和转换的参考数据和输入逻辑数据，以检测它们是否彼此一致。 用于确定比较定时的时钟信号也被时钟信号分频电路划分为n个时钟信号，这些n个时钟信号相移一个时隙并且以n个时隙的周期发生。 通过这些分开的时钟信号，从比较输出电路中取出与其相对应的比较器的输出。

公开(公告)号：US20120045277A1

公开(公告)日：2012-02-23

申请号：US13266258

申请日：2010-04-21

Applicant: Susumu Sumida ,  Yuji Sumida

Inventor： Susumu Sumida ,  Yuji Sumida

IPC: F16B2/16

CPC classification number: F16G13/18 ,  F16B2/16 ,  F16B7/04 ,  F16G13/06 ,  Y10T403/7064

Abstract: Disclosed is a device configured to clamp a bar member (2) by inserting the bar member (2) through a through hole formed by bending a chain (1) including inner link plates (4) and outer link plates (3) connected via pins (5) so as to be freely bendable into a saw-tooth shape, fixing an end (A) of the chain 1 and clamping the bar member (2) by the pins (5) in a state of blocking the bar member (2) from being pulled out toward the other free end (B), the bar member (2) can be strongly clamped by forming the pins (5, 5 . . . ) in non-circular shape in cross section.

Abstract translation: 公开了一种被配置为通过将杆构件（2）插入通过弯曲形成的通孔而形成的杆构件（2）的装置，所述通孔包括通过销连接的内链板（4）和外链板（3）的链条 （5），可自由弯曲成锯齿形状，固定链条1的端部（A）并通过销（5）将杆件（2）夹紧在杆件（2）的状态 ）从向另一个自由端（B）拉出时，通过以横截面形成非圆形形状的销（5,5 ...）可以强力地夹紧杆件（2）。

公开(公告)号：US4790791A

公开(公告)日：1988-12-13

申请号：US64009

申请日：1987-06-19

Applicant: Susumu Sumida ,  Atsuo Kamata ,  Fuyuki Yoshii

Inventor： Susumu Sumida ,  Atsuo Kamata ,  Fuyuki Yoshii

IPC: F16D3/12 ,  F16D3/76 ,  F16F15/12 ,  F16F15/126

CPC classification number: F16D3/76 ,  Y10T464/10

Abstract: A ring-shaped coupling comprising an inner ring, a rubber ring whose outer circumferential surface is divided by a circular groove into two conical surfaces each flaring toward the center in the axial directions and whose inner circumferential surface forming one solid surface is made to adhere by vulcanization to the outer circumferential surface of the inner ring, a pair of outer rings which are placed facing each other in the axial direction and a joining number. One of the inner circumferential surfaces of the outer rings having the shape of a conical surface flaring toward the other, and to the inner circumferential surfaces adhering by vulcanization the two conical sections of the outer circumferential surface of the rubber ring. The joining member puts the outer rings close to each other in the axial direction and fixes them in place in such a manner as to compress the rubber ring under the outer rings.

Abstract translation: 一种环形联轴器，包括内圈，其外周表面被圆形槽分成两个锥形表面的橡胶环，每个锥形表面各自向轴向方向的中心扩张，并且其形成一个固体表面的内圆周表面被附着 对内圈的外周面进行硫化，沿轴向彼此相对放置的一对外圈和接合数。 外环的一个内圆周表面具有朝向另一个的锥形表面的形状，以及通过硫化粘附橡胶环的外周表面的两个锥形部分的内周表面。 接合构件将外圈沿轴向彼此靠近，并将它们固定在适当位置，以压缩外圈下方的橡胶环。

公开(公告)号：US4486381A

公开(公告)日：1984-12-04

申请号：US368436

申请日：1982-04-14

Applicant: Hirukawa Koji ,  Susumu Sumida

Inventor： Hirukawa Koji ,  Susumu Sumida

IPC: G21C7/00 ,  G21C7/08 ,  G21C7/32 ,  G21C7/36 ,  G21D3/04

CPC classification number: G21C7/32 ,  G21C7/36 ,  Y02E30/31 ,  Y02E30/39

Abstract: A power control apparatus of a boiling water atomic reactor for transferring the atomic reactor to a low power stand-by operation when a load of a generator is rejected. The necessity of insertion of control rods into a core is decided in accordance with the state of the atomic reactor when a load rejection occurs. When the insertion of control rods is required selected control rods are inserted into the core and a core flow rate is reduced to transfer the atomic reactor to the low power stand-by operation. When the insertion of control rods is not necessary only the reduction of core flow rate is performed.

Abstract translation: 一种沸水原子反应器的功率控制装置，用于在发电机的负载被拒绝时将原子反应堆转移到低功率待机操作。 当发生负载抑制时，根据原子反应堆的状态来决定将控制棒插入芯中的必要性。 当需要插入控制棒时，选择的控制棒插入到芯中，并且减少芯流量以将原子反应器转移到低功率待机操作。 当不需要插入控制棒时，仅进行芯流量的降低。

公开(公告)号：US4310802A

公开(公告)日：1982-01-12

申请号：US69348

申请日：1979-08-24

Applicant: Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Takashi Tokuno

Inventor： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Takashi Tokuno

IPC: G06F11/22 ,  G01R31/3183 ,  G01R31/319 ,  G06F1/06 ,  H03K5/135 ,  H03K5/156 ,  H03K5/22

CPC classification number: G01R31/31922 ,  H03K5/156 ,  G01R31/31928

Abstract: Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.

Abstract translation: 输入逻辑数据由每个时隙的数据分割电路顺序划分成n个数据列，每个数据块具有n个时隙长度。 可以任意定时的时钟信号由时钟分频电路划分成n个时钟信号，这些时钟信号在相位上分离一个时隙并且以n个时隙的周期发生。 在逻辑电路中，划分的时钟信号由对应的分割数据串进行控制，并且受控时钟信号由复用电路进行时间复用，从而获得输入逻辑数据已被时钟信号定时的输出数据 。