公开(公告)号：US4310802A

公开(公告)日：1982-01-12

申请号：US69348

申请日：1979-08-24

申请人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Takashi Tokuno

发明人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Takashi Tokuno

IPC分类号： G06F11/22 ,  G01R31/3183 ,  G01R31/319 ,  G06F1/06 ,  H03K5/135 ,  H03K5/156 ,  H03K5/22

CPC分类号： G01R31/31922 ,  H03K5/156 ,  G01R31/31928

摘要： Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.

摘要翻译： 输入逻辑数据由每个时隙的数据分割电路顺序划分成n个数据列，每个数据块具有n个时隙长度。 可以任意定时的时钟信号由时钟分频电路划分成n个时钟信号，这些时钟信号在相位上分离一个时隙并且以n个时隙的周期发生。 在逻辑电路中，划分的时钟信号由对应的分割数据串进行控制，并且受控时钟信号由复用电路进行时间复用，从而获得输入逻辑数据已被时钟信号定时的输出数据 。

公开(公告)号：US4270116A

公开(公告)日：1981-05-26

申请号：US69347

申请日：1979-08-24

申请人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Masao Shimizu ,  Toshiaki Wakita

发明人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Masao Shimizu ,  Toshiaki Wakita

IPC分类号： G01R31/28 ,  G06F7/02 ,  G06F7/04 ,  G06F11/22

CPC分类号： G06F7/02

摘要： Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.

摘要翻译： 参考逻辑数据由每个时隙的数据分割电路在空间上划分，并且分割的数据被转换成数据，每个数据具有连续的有效周期。 通过比较器比较分割和转换的参考数据和输入逻辑数据，以检测它们是否彼此一致。 用于确定比较定时的时钟信号也被时钟信号分频电路划分为n个时钟信号，这些n个时钟信号相移一个时隙并且以n个时隙的周期发生。 通过这些分开的时钟信号，从比较输出电路中取出与其相对应的比较器的输出。

公开(公告)号：US4402081A

公开(公告)日：1983-08-30

申请号：US195079

申请日：1980-10-08

申请人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Masao Shimizu

发明人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Masao Shimizu

IPC分类号： G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/319 ,  G11C29/10 ,  G11C29/56 ,  G06F11/00

CPC分类号： G11C29/56 ,  G01R31/31921 ,  G01R31/31813

摘要： A semiconductor memory test pattern generating apparatus in which an instruction memory is read out, assigning an address by a program counter, and instructions thus read out are decoded and executed to generate a test pattern. A start address and a stop address and index data indicating the number of times of executing an area defined by the start and stop addresses are stored in a loop memory. During the operation of the program counter the start and stop addresses and the index data are read out from the loop memory and loaded in a register group. When the program counter coincides with the loaded stop address, the setting of the program counter to the loaded start address is executed by the number of times indicated by the loaded index data, and in the last execution the next address of the loop memory is read out.

摘要翻译： 一种半导体存储器测试图形生成装置，其中读出指令存储器，通过程序计数器分配地址和由此读出的指令被解码和执行以产生测试图案。 指示由起始和停止地址定义的区域执行次数的起始地址和停止地址和索引数据被存储在循环存储器中。 在程序计数器的操作期间，从循环存储器中读出起始和停止地址和索引数据，并加载到寄存器组中。 当程序计数器与加载的停止地址一致时，程序计数器对加载的起始地址的设置由加载的索引数据指示的次数执行，在最后一次执行中循环存储器的下一个地址被读取 出来

公开(公告)号：US4573120A

公开(公告)日：1986-02-25

申请号：US547461

申请日：1983-11-01

申请人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Turo Takehisa ,  Katsumi Shimada

发明人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Turo Takehisa ,  Katsumi Shimada

IPC分类号： G05B15/02 ,  G06F13/37 ,  G06F13/42 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F13/4247

摘要： A central processing unit is cascade-connected with a plurality of I/O units, and a bus interconnecting them comprises a plurality of data lines for transmitting a control command signal, an address signal and a data signal on a time shared basis, a plurality of tag lines, each transmitting a tag signal indicating which one of the signals is provided on the data lines, and a clock line for transmitting a clock signal for these signals.

摘要翻译： 中央处理单元与多个I / O单元级联连接，并且其互连的总线包括用于在时间共享的基础上发送控制命令信号，地址信号和数据信号的多条数据线，多个 的标签线，每个发送指示在数据线上提供哪个信号的标签信号，以及用于发送这些信号的时钟信号的时钟线。

公开(公告)号：US4216533A

公开(公告)日：1980-08-05

申请号：US23458

申请日：1979-03-23

申请人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Katsumi Shimada

发明人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Katsumi Shimada

IPC分类号： G06F11/22 ,  G01R31/3183 ,  G01R31/319 ,  G06F7/78 ,  G06F12/06 ,  H03K3/78 ,  G11C11/40

CPC分类号： G06F7/78 ,  G01R31/31919

摘要： A plurality of low-speed memories having stored therein a plurality of patterns and first and second high-speed memories of higher operating speed than the low-speed memories are provided. One of the first and second high-speed memories is read to obtain output patterns and, at the same time, the plurality of low-speed memories are simultaneously read and the read-out data are successively written in the other high-speed memory alternately with each other. Upon completion of pattern generation from the one high-speed memory, pattern generation from the other high-speed memory is achieved.

摘要翻译： 提供了多个存储有多个图案的多个低速存储器以及比低速存储器更高的操作速度的第一和第二高速存储器。 读取第一和第二高速存储器中的一个以获得输出模式，并且同时多个低速存储器被同时读取，并且读出的数据被交替地写入另一个高速存储器 与彼此。 在从一个高速存储器完成图案生成后，实现了来自另一个高速存储器的图案生成。