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    Semiconductor integrated circuit system, semiconductor integrated circuit and method for driving semiconductor integrated circuit system
    1.
    发明授权
    Semiconductor integrated circuit system, semiconductor integrated circuit and method for driving semiconductor integrated circuit system 失效
    半导体集成电路系统，半导体集成电路及半导体集成电路系统驱动方法

    公开(公告)号：US06393577B1

    公开(公告)日：2002-05-21

    申请号：US09115716

    申请日：1998-07-15

    申请人： Hironori Akamatsu ,  Toru Iwata

    发明人： Hironori Akamatsu ,  Toru Iwata

    IPC分类号： G06F1342

    CPC分类号： G06F1/025 ,  G06F1/10 ,  H03L7/06

    摘要： The present invention provides a semiconductor integrated circuit system, having one master chip and a plurality of slave chips, for performing data transfer under a control of a predetermined clock. The system includes: a detection section for detecting a change in a state of the semiconductor integrated circuit system and for producing information indicating the detection result, the state including at least one of temperature and source voltage; and at least one clock phase adjustment section for receiving the information and for adjusting a phase of a clock used in transferring data output by the slave chip based on the information.

    摘要翻译： 本发明提供一种具有一个主芯片和多个从芯片的半导体集成电路系统，用于在预定时钟的控制下执行数据传输。 该系统包括：检测部分，用于检测半导体集成电路系统的状态变化，并产生指示检测结果的信息，该状态包括温度和电源电压中的至少一个; 以及至少一个时钟相位调整部分，用于接收所述信息并且用于根据所述信息调整用于传送由所述从芯片输出的数据所使用的时钟的相位。

    Static random access memory capable of both reducing power consumption and retaining data at standby-time
    2.
    发明授权
    Static random access memory capable of both reducing power consumption and retaining data at standby-time 失效
    静态随机存取存储器能够在待机时减少功耗并保留数据

    公开(公告)号：US5734604A

    公开(公告)日：1998-03-31

    申请号：US739392

    申请日：1996-10-29

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

    CPC分类号： G11C11/412 ,  G11C11/417

    摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

    摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

    Data holding circuit
    5.
    发明授权
    Data holding circuit 失效
    数据保持电路

    公开(公告)号：US5757702A

    公开(公告)日：1998-05-26

    申请号：US739363

    申请日：1996-10-29

    申请人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

    发明人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

    IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419 ,  G11C11/412

    摘要： A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.

    摘要翻译： 存储单元包括通过其中一个反相器的输出节点和另一个反相器的输入节点以及第一和第二晶体管彼此连接的第一反相器和第二反相器。 在其栅电极处与字线连接的晶体管中的每一个插入在位线对和每个存储器节点之一之间。 该数据保持电路包括用于将用于驱动该对反相器的存储单元电源电位增加到高于施加到外围电路的电源电位的元件，或者用于将用于驱动该对反相器的接地电压降低到低于 施加到外围电路的接地电压。

    Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system
    6.
    发明授权
    Semiconductor integrated circuit with voltage-detecting circuit and signal transmitting and receiving system 失效
    具有电压检测电路和信号发射和接收系统的半导体集成电路

    公开(公告)号：US06944003B2

    公开(公告)日：2005-09-13

    申请号：US10365527

    申请日：2003-02-13

    申请人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

    发明人： Hirokazu Sugimoto ,  Takashi Hirata ,  Hironori Akamatsu ,  Toru Iwata ,  Satoshi Takahashi

    IPC分类号： G01R31/28 ,  H01L21/66 ,  H02H9/04 ,  H02H3/24

    CPC分类号： H02H9/046

    摘要： A first semiconductor integrated circuit is connected to a second semiconductor integrated circuit with a cable. In the first semiconductor integrated circuit, when a power supply voltage becomes less than a set voltage detection level, a voltage-detecting circuit outputs a voltage-detected signal to lower the voltage of the cable and to stop the operation. The second semiconductor integrated circuit detects the decrease in the voltage of the cable to recognize the halt of the operation of the first semiconductor integrated circuit. In the first semiconductor integrated circuit thus configured, in testing the operation under low-voltage conditions in which the power supply voltage is less than the set voltage detection level, the voltage-detecting circuit receives a control signal from an external terminal to stop the operation forcibly. Consequently, even when the power supply voltage is made lower than the set voltage-detecting level, the first semiconductor integrated circuit properly operates until the power supply voltage reaches a predetermined lower limit of operating voltage. Thus, evaluation of operation is possible under low-voltage conditions.

    摘要翻译： 第一半导体集成电路通过电缆连接到第二半导体集成电路。 在第一半导体集成电路中，当电源电压变得小于设定电压检测电平时，电压检测电路输出电压检测信号来降低电缆的电压并停止工作。 第二半导体集成电路检测电缆的电压的降低以识别第一半导体集成电路的操作停止。 在这样配置的第一半导体集成电路中，在电源电压小于设定电压检测电平的低电压条件下进行测试时，电压检测电路从外部端子接收控制信号，停止动作 强制。 因此，即使电源电压低于设定电压检测电平，第一半导体集成电路也可以正常工作，直到电源电压达到预定的工作电压下限。 因此，在低电压条件下可以进行运行评估。

    Static random access memory capable of reducing stendly power consumption and off-leakage current
    8.
    发明授权
    Static random access memory capable of reducing stendly power consumption and off-leakage current 失效
    静态随机存取存储器能够降低待机功耗和漏电流

    公开(公告)号：US5764566A

    公开(公告)日：1998-06-09

    申请号：US893682

    申请日：1997-07-11

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

    CPC分类号： G11C11/412 ,  G11C11/417

    摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

    摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

    Semiconductor device having a plurality of semiconductor chips connected together by a bus
    9.
    发明授权
    Semiconductor device having a plurality of semiconductor chips connected together by a bus 有权
    具有通过总线连接在一起的多个半导体芯片的半导体装置

    公开(公告)号：US06633607B1

    公开(公告)日：2003-10-14

    申请号：US09249695

    申请日：1999-02-12

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

    IPC分类号： H03K904

    CPC分类号： H03M9/00 ,  H04L25/49

    摘要： A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.

    摘要翻译： 一种半导体器件包括：发送部分; 以及接收部分，其中所述发送部分和所述接收部分通过总线相互连接，所述发送部分包括用于对包括多个比特的数据进行编码的编码部分，以产生指示至少的位置的比特位置信息 从包含在数据中的多个比特中选择一个比特，以及用于将比特位置信息输出到总线上的输出部分，并且接收部分包括用于从总线接收比特位置信息的输入部分和解码 用于解码位位置信息以产生数据。

    Clock generation circuit and semiconductor integrated circuit
    10.
    发明授权
    Clock generation circuit and semiconductor integrated circuit 有权
    时钟发生电路和半导体集成电路

    公开(公告)号：US06191632B1

    公开(公告)日：2001-02-20

    申请号：US09359727

    申请日：1999-07-23

    申请人： Toru Iwata ,  Hironori Akamatsu

    发明人： Toru Iwata ,  Hironori Akamatsu

    IPC分类号： H03K300

    CPC分类号： H03K5/153 ,  G06F1/10 ,  H03K5/133

    摘要： A clock generation circuit comprises a clock wiring having opposed first and second ends, through which a clock is transmitted from the first end to the second end, and a plurality of clock phase adjustment circuits for generating internal clocks in accordance with the clock supplied from the clock wiring. Each of the clock phase adjustment circuits comprises a first-end side terminal and a second-end side terminal which are connected to a first-end side point and a second-end side point of the circuit, respectively, the points being positioned on both sides of a reference point of the clock wiring; a delay line for delaying a clock supplied from one of the terminals and outputting an internal clock; and a delay control circuit for performing feedback control on a delay of the clock in the delay means in accordance with the phase of the clock supplied from the other terminal so that the phase of the internal clock matches the phase of the clock at the reference point of the cock wiring. Therefore, regardless of the distances from the first end (clock input end) of the clock wiring to the respective clock phase adjustment circuits, internal clocks of the same phase are output from the clock phase adjustment circuits.

    摘要翻译： 时钟发生电路包括具有相对的第一和第二端的时钟布线，通过该时钟布线从第一端发送到第二端，以及多个时钟相位调整电路，用于根据从第一端提供的时钟产生内部时钟 时钟接线。 每个时钟相位调整电路包括分别连接到电路的第一端侧点和第二端侧点的第一端侧端子和第二端侧端子，所述点位于两者上 侧面参考点的时钟布线; 用于延迟从一个终端提供的时钟并输出内部时钟的延迟线; 以及延迟控制电路，用于根据从另一个终端提供的时钟的相位对延迟装置中的时钟的延迟执行反馈控制，使得内部时钟的相位与参考点的时钟的相位匹配 的公鸡接线。 因此，不管从时钟线的第一端（时钟输入端）到各时钟相位调整电路的距离，从时钟相位调整电路输出同相的内部时钟。