公开(公告)号：US09612989B2

公开(公告)日：2017-04-04

申请号：US13997539

申请日：2010-12-24

申请人： Shuhei Eguchi ,  Ryo Yamagata ,  Takashi Todaka

发明人： Shuhei Eguchi ,  Ryo Yamagata ,  Takashi Todaka

IPC分类号： G06F13/40 ,  H04L12/935 ,  G06F13/36

CPC分类号： G06F13/4022 ,  G06F13/36 ,  H04L49/30

摘要： The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.

公开(公告)号：US20140006679A1

公开(公告)日：2014-01-02

申请号：US13997539

申请日：2010-12-24

申请人： Shuhei Eguchi ,  Ryo Yamagata ,  Takashi Todaka

发明人： Shuhei Eguchi ,  Ryo Yamagata ,  Takashi Todaka

IPC分类号： G06F13/40

CPC分类号： G06F13/4022 ,  G06F13/36 ,  H04L49/30

摘要： The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.

摘要翻译： 本发明消除了使用PCIe交换机的路由控制中总线数量的不足。 系统端口地址（SPA）与目的地总线号相关联，并分配给连接到服务器和设备的端口（外部端口）。 当在外部端口接收到从服务器或设备发送的数据包时，确定与具有数据包的目标总线号码相对应的系统端口地址（SPA），并将SPA作为标签添加到数据包。 此SPA用于路由连接交换机的端口（内部端口）之间发送的数据包。 当分组到达目标服务器或设备连接的外部端口时，具有分组的目的地总线号码用于将数据包发送到连接到外部端口的服务器或设备。

公开(公告)号：US20130254453A1

公开(公告)日：2013-09-26

申请号：US13989999

申请日：2010-11-29

申请人： Kazuki Sato ,  Takashi Todaka ,  Ryo Takase

发明人： Kazuki Sato ,  Takashi Todaka ,  Ryo Takase

IPC分类号： G06F13/40

CPC分类号： G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F2213/0024 ,  G06F2213/0026

摘要： A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O devices to a computer via a PCIe switch. A switch with which a computer and I/O devices are connected includes: a first PCI-PCI bridge which is positioned on the computer side; a second PCI-PCI bridge which is positioned on the I/O device side; trapper units which trap packet data which is inputted into the switch; a packet routing unit which transfers packet data to the I/O devices; and a management processor which is connected to the trapper units and provides the computer a virtual PCI-PCI bridge and a virtual link by execution of a program. The trapper units adjudicate the destination of the packet data which is transferred from the computer.

摘要翻译： 公开了一种系统和方法，以防止通过经由PCIe交换机将I / O设备连接到计算机来构建PCIe拓扑结构时可以连接的I / O设备的数量减少。 连接有计算机和I / O设备的开关包括：位于计算机侧的第一PCI-PCI桥; 位于I / O设备侧的第二PCI-PCI桥; 捕获输入到开关中的分组数据的捕获器单元; 将分组数据传送到I / O设备的分组路由单元; 以及管理处理器，其连接到捕获器单元并且通过执行程序向计算机提供虚拟PCI-PCI桥接器和虚拟链路。 陷阱单元判定从计算机传送的分组数据的目的地。

公开(公告)号：US08200934B2

公开(公告)日：2012-06-12

申请号：US11865669

申请日：2007-10-01

申请人： Hironori Kasahara ,  Keiji Kimura ,  Takashi Todaka ,  Tatsuya Kamei ,  Toshihiro Hattori

发明人： Hironori Kasahara ,  Keiji Kimura ,  Takashi Todaka ,  Tatsuya Kamei ,  Toshihiro Hattori

IPC分类号： G06F12/00

CPC分类号： G06F15/167

摘要： To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.

摘要翻译： 为了减少处理器核心之间的数据传输的开销并提高处理器的处理能力，提供了一种处理器，包括：用于执行计算处理的CPU; 用于存储数据的内部存储器; 以及数据传送单元，用于在内部存储器和共享存储器之间执行数据传送，其中：数据传送单元包括：命令链模块，用于执行由包括数据传送指令的多个命令形成的命令序列; 以及监视器模块，用于读取预先在内部存储器中设置的数据并重复监视数据，直到数据的比较值和值变得彼此相等时，当这样读取的命令序列的多个命令之一是 预定命令 命令链模块在监控模块完成监控后，在命令序列中执行下一个命令。

公开(公告)号：US09396150B2

公开(公告)日：2016-07-19

申请号：US13989999

申请日：2010-11-29

申请人： Kazuki Sato ,  Takashi Todaka ,  Ryo Takase

发明人： Kazuki Sato ,  Takashi Todaka ,  Ryo Takase

IPC分类号： G06F13/40

CPC分类号： G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F2213/0024 ,  G06F2213/0026

摘要： A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O devices to a computer via a PCIe switch. A switch with which a computer and I/O devices are connected includes: a first PCI-PCI bridge which is positioned on the computer side; a second PCI-PCI bridge which is positioned on the I/O device side; trapper units which trap packet data which is inputted into the switch; a packet routing unit which transfers packet data to the I/O devices; and a management processor which is connected to the trapper units and provides the computer a virtual PCI-PCI bridge and a virtual link by execution of a program. The trapper units adjudicate the destination of the packet data which is transferred from the computer.

摘要翻译： 公开了一种系统和方法，以防止通过经由PCIe交换机将I / O设备连接到计算机来构建PCIe拓扑结构时可以连接的I / O设备的数量减少。 连接有计算机和I / O设备的开关包括：位于计算机侧的第一PCI-PCI桥; 位于I / O设备侧的第二PCI-PCI桥; 捕获输入到开关中的分组数据的捕获器单元; 将分组数据传送到I / O设备的分组路由单元; 以及管理处理器，其连接到捕获器单元并且通过执行程序向计算机提供虚拟PCI-PCI桥接器和虚拟链路。 陷阱单元判定从计算机传送的分组数据的目的地。

公开(公告)号：US20080086617A1

公开(公告)日：2008-04-10

申请号：US11865669

申请日：2007-10-01

申请人： Hironori KASAHARA ,  Keiji Kimura ,  Takashi Todaka ,  Tatsuya Kamei ,  Toshihiro Hattori

发明人： Hironori KASAHARA ,  Keiji Kimura ,  Takashi Todaka ,  Tatsuya Kamei ,  Toshihiro Hattori

IPC分类号： G06F13/00

CPC分类号： G06F15/167

摘要： To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.

摘要翻译： 为了减少处理器核心之间的数据传输的开销并提高处理器的处理能力，提供了一种处理器，包括：用于执行计算处理的CPU; 用于存储数据的内部存储器; 以及数据传送单元，用于在内部存储器和共享存储器之间执行数据传送，其中：数据传送单元包括：命令链模块，用于执行由包括数据传送指令的多个命令形成的命令序列; 以及监视器模块，用于读取预先在内部存储器中设置的数据并重复监视数据，直到数据的比较值和值变得彼此相等时，当这样读取的命令序列的多个命令之一是 预定命令 命令链模块在监控模块完成监控后，在命令序列中执行下一个命令。

公开(公告)号：US07882277B2

公开(公告)日：2011-02-01

申请号：US12172891

申请日：2008-07-14

申请人： Takashi Todaka

发明人： Takashi Todaka

IPC分类号： G06F13/28 ,  G06F13/00

CPC分类号： G06F11/1443

摘要： A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system.

摘要翻译： 处理器包括能够执行预定的算术处理的CPU，由CPU访问的存储器，以及能够通过代替CPU来控制与存储器的数据传送的数据传送单元。 数据传送单元设置有用于通过执行预设的命令链来连续执行数据传送的命令链单元，以及用于在由命令链单元进行数据传送期间发生传输错误的情况下执行重试处理的重试控制器。 然后，在执行命令链之后，数据传送单元将与传送错误有关的命令报告给CPU，从而减少错误处理的中断次数，并提高系统的性能。