公开(公告)号：US08558460B2

公开(公告)日：2013-10-15

申请号：US13146086

申请日：2010-01-25

申请人： Masaru Nonomura ,  Hiroshi Haji ,  Kiyoshi Arita

发明人： Masaru Nonomura ,  Hiroshi Haji ,  Kiyoshi Arita

IPC分类号： H01J7/24

CPC分类号： H01J37/32935

摘要： A plasma processing apparatus includes: a vacuum chamber; a plasma processing execution portion; a discharge state detecting unit; a window portion; a camera; a first storing portion; a second storing portion; and an image data extracting unit. The image data extracting unit extracts at least moving image data, which show the generation state of the abnormal discharge, from the first storing portion and stores the extracted moving image data in the second storing portion when the discharge state detecting unit detects the abnormal discharge.

摘要翻译： 一种等离子体处理装置，包括：真空室; 等离子体处理执行部分; 放电状态检测单元; 窗口部分; 相机; 第一存储部分; 第二存储部分; 和图像数据提取单元。 当排出状态检测单元检测到异常放电时，图像数据提取单元至少从第一存储部分中提取表示异常放电的生成状态的运动图像数据并将提取的运动图像数据存储在第二存储部分中。

公开(公告)号：US07629228B2

公开(公告)日：2009-12-08

申请号：US11193487

申请日：2005-08-01

申请人： Hiroshi Haji ,  Kiyoshi Arita ,  Teruaki Nishinaka

发明人： Hiroshi Haji ,  Kiyoshi Arita ,  Teruaki Nishinaka

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.

摘要翻译： 在其中形成有多个半导体器件的半导体晶片的掩模放置侧表面上，设置掩模，同时定义用于将半导体晶片切割成各自的分离的半导体器件的切割线和有缺陷的半导体器件的表面 在各个半导体器件中部分曝光，然后将等离子体蚀刻施加到半导体晶片的掩模放置侧表面，以便沿着限定的切割线将半导体晶片切割成各个半导体器件，并且将暴露部分 去除有缺陷的半导体器件，以形成作为有缺陷的半导体器件区分标记的去除部分。

公开(公告)号：US07074720B2

公开(公告)日：2006-07-11

申请号：US10178444

申请日：2002-06-21

申请人： Kiyoshi Arita ,  Tetsuhiro Iwai ,  Hiroshi Haji ,  Shoji Sakemi

发明人： Kiyoshi Arita ,  Tetsuhiro Iwai ,  Hiroshi Haji ,  Shoji Sakemi

IPC分类号： H01L21/302 ,  H01L21/3065

CPC分类号： H01L21/6835 ,  H01J37/3244 ,  H01J37/32532 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/67092 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/6834

摘要： In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion 18a formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member 17 for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion 18b formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.

摘要翻译： 在等离子体处理装置中，将具有三维网状结构的陶瓷多孔物质用于电极部件17的材料，其中三维网状结构的三维网状连续地设置有由含有氧化铝的陶瓷构成的框架部分18a， 等离子体产生用电极的气体供给口的前表面的等离子体处理装置和等离子体产生用气体通过三维网状结构中不规则形成的孔部18b。 因此，供给气体的分布均匀，以防止异常放电，从而可以进行不变化的均匀蚀刻。

公开(公告)号：US20060019416A1

公开(公告)日：2006-01-26

申请号：US11183739

申请日：2005-07-19

申请人： Kiyoshi Arita ,  Hiroshi Haji ,  Kazuhiro Noda ,  Akira Nakagawa ,  Teruaki Nishinaka

发明人： Kiyoshi Arita ,  Hiroshi Haji ,  Kazuhiro Noda ,  Akira Nakagawa ,  Teruaki Nishinaka

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： G03F7/70433 ,  H01L21/78

摘要： With use of a length-dimension of a second-line-segment of a unit-device-formation-region as an arrangement interval, a plurality of parallel lines are disposed in a device-formation-effective-region on a wafer so as to form a plurality of parallel-line-partition-regions, the unit-device-formation-regions are arranged in each of the parallel-line-partition-regions independently of and separately from other parallel-line-partition-regions so that the acquisition number of the unit-device-formation-regions is maximized, and an arrangement of the respective unit-device-formation-regions in the respective parallel-line-partition-regions is determined as an arrangement of the entire device-formation-effective-region.

公开(公告)号：US06784112B2

公开(公告)日：2004-08-31

申请号：US10114320

申请日：2002-04-03

申请人： Kiyoshi Arita ,  Tetsuhiro Iwai ,  Hiroshi Haji ,  Shoji Sakemi

发明人： Kiyoshi Arita ,  Tetsuhiro Iwai ,  Hiroshi Haji ,  Shoji Sakemi

IPC分类号： H01L21302

CPC分类号： H01L21/3065

摘要： A surface treatment method for thinning a silicon based substrate obtains a milky-dull color on an overall surface uniformly of the silicon based substrate. To be more specific, a surface opposite to a circuit-formed surface is mechanically polished, then the surface is etched using inert gas such as argon gas for producing plasma. This etching forms micro dimples uniformly on the surface. Next, the surface is further etched using fluorine based gas for producing plasma. This etching obtains a milky-dull color uniformly on the surface. As a result, printed marks on the surface can be read with ease, and pick-up errors in die-bonding can be reduced.

摘要翻译： 用于使硅基衬底变薄的表面处理方法在硅基衬底的整个表面上均匀地获得乳白色的颜色。 更具体地说，与电路形成表面相对的表面被机械抛光，然后使用诸如氩气的惰性气体蚀刻表面，以产生等离子体。 该蚀刻在表面上均匀地形成微凹坑。 接下来，使用氟基气体进一步蚀刻表面以产生等离子体。 该蚀刻在表面上均匀地获得乳白色的颜色。 结果，可以容易地读取表面上的印刷标记，并且可以降低芯片接合中的拾取误差。

公开(公告)号：US5288008A

公开(公告)日：1994-02-22

申请号：US983026

申请日：1992-11-30

申请人： Hiroshi Haji ,  Kiyoshi Arita

发明人： Hiroshi Haji ,  Kiyoshi Arita

IPC分类号： H01L21/60

CPC分类号： H01L24/86 ,  H01L2224/16 ,  H01L2224/7965 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14

摘要： A process for manufacturing electronic components known as TAB method comprises a process employing a single apparatus for forming bumps in a chip, a process of inner lead bonding for bonding said bumps to leads of a film carrier, and a process of outer lead bonding for bonding the leads to a circuit board after punching said film carrier. The bumps are formed by plating means or by stud bump means using a capillary tool. In another aspect of the invention there is provided an apparatus by which it is possible to form the bumps and to perform the inner lead bonding in a single apparatus. The capillary tool for forming the inner lead bonding and a pressing tool for the inner lead bonding are replaceably and selectively mounted to be held on a horn. Also, there are provided a pickup head for moving the chip furnished in a chip feeding unit to the chip stage and a moving table for moving the chip stage. The capillary tool is held by the horn, and the bumps are formed in the chip on the chip stage while pulling out a wire from the capillary tool. Next, the pressing tool is manually mounted to be held by the horn in place of the capillary tool, and the leads of the film carrier on the chip stage are bonded to the bumps formed in the chip.

摘要翻译： 用于制造称为TAB方法的电子部件的方法包括使用单个装置在芯片中形成凸块的工艺，用于将所述凸块接合到薄膜载体的引线的内部引线接合的工艺，以及用于接合的外部引线接合 在冲压所述胶片载体之后导向电路板。 凸块由电镀装置或使用毛细管工具的螺柱凸块形成。 在本发明的另一方面，提供了一种可以在单个装置中形成凸块并执行内引线接合的装置。 用于形成内部引线接合的毛细管工具和用于内部引线接合的按压工具可更换和选择性地安装以保持在喇叭上。 此外，还提供了一种用于将设置在芯片馈送单元中的芯片移动到芯片级的拾取头和用于移动芯片级的移动台。 毛细管工具由喇叭保持，并且在从毛细管工具拉出线材时，在芯片台上的芯片中形成凸块。 接下来，代替毛细管工具手动地安装按压工具以由喇叭保持，并且芯片台上的胶片载体的引线接合到芯片中形成的凸块。

公开(公告)号：US07927973B2

公开(公告)日：2011-04-19

申请号：US11663543

申请日：2005-10-04

申请人： Hiroshi Haji ,  Kiyoshi Arita ,  Akira Nakagawa ,  Kazuhiro Noda

发明人： Hiroshi Haji ,  Kiyoshi Arita ,  Akira Nakagawa ,  Kazuhiro Noda

IPC分类号： H01L21/78 ,  H01L21/308

CPC分类号： H01L21/78

摘要： In a semiconductor wafer including a plurality of imaginary-divided-regions which are partitioned by imaginary-dividing-lines that are respectively arranged in a grid-like arrangement on the semiconductor wafer and a circumferential line that is the outer periphery outline of the semiconductor wafer, a mask is placed so as to expose an entirety of surfaces of the wafer corresponding to respective removal-regions. The removal-regions are regions in approximately triangular form partitioned by the circumferential line of the wafer and the imaginary-dividing-lines. Then, plasma etching is performed on a mask placement-side surface of the wafer, by which the semiconductor wafer is divided into the individual semiconductor devices along dividing lines while portions corresponding to the removal-regions of the wafer are removed.

摘要翻译： 在半导体晶片中，具有分别由在半导体晶片上排列成格子状的虚拟分割线分隔的多个虚分割区域和作为半导体晶片的外周轮廓的周向线 放置掩模以使与相应的移除区域对应的晶片的整个表面露出。 去除区域是由晶片的圆周线和假想分界线分隔的大致三角形的区域。 然后，在晶片的掩模放置侧表面上执行等离子体蚀刻，通过该等离子体蚀刻，半导体晶片沿着划分线被划分成各个半导体器件，同时去除与晶片的去除区域相对应的部分。

公开(公告)号：US07767551B2

公开(公告)日：2010-08-03

申请号：US12160143

申请日：2007-10-05

申请人： Kiyoshi Arita ,  Hiroshi Haji

发明人： Kiyoshi Arita ,  Hiroshi Haji

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  B23K2103/42 ,  B23K2103/50 ,  H01L24/743 ,  H01L2224/743 ,  H01L2924/12042 ,  H01L2924/00

摘要： After a film layer 6 formed from a die attach film 4 and a UV tape 5 has been provided as a mask on a semiconductor wafer 1, boundary trenches 7 for partitioning semiconductor elements 2 formed on a circuit pattern formation surface 1a are formed in the film layer 6, thereby making a surface 1c of a semiconductor wafer 1 exposed. The exposed surface 1c of the semiconductor wafer 1 in the boundary trenches 7 is etched by means of plasma of a fluorine-based gas, and the semiconductor wafer 1 is sliced into semiconductor chips 1′ along the boundary trenches 7.

摘要翻译： 在半导体晶片1上设置由芯片附着膜4和UV带5形成的膜层6作为掩模，形成在电路图案形成表面1a上形成的半导体元件2的边界沟槽7形成在膜 层6，从而使半导体晶片1的表面1c露出。 边界槽7中的半导体晶片1的露出面1c利用氟系气体的等离子体进行蚀刻，半导体晶片1沿着边界沟槽7切割成半导体芯片1'。

公开(公告)号：US07138034B2

公开(公告)日：2006-11-21

申请号：US10176804

申请日：2002-06-21

申请人： Kiyoshi Arita ,  Tetsuhiro Iwai ,  Hiroshi Haji ,  Shoji Sakemi ,  Taiji Matano ,  Nobuhiro Satou

发明人： Kiyoshi Arita ,  Tetsuhiro Iwai ,  Hiroshi Haji ,  Shoji Sakemi ,  Taiji Matano ,  Nobuhiro Satou

IPC分类号： H01L21/00

CPC分类号： C23C16/45568 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32532 ,  H01L21/3065

摘要： In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.

摘要翻译： 在等离子体处理装置中，使用具有三维网状结构的陶瓷多孔物质，其中由含有氧化铝的陶瓷形成的框架部分连续地设置为三维网络，用于等离子体处理装置的电极部件的材料 附着于等离子体产生用电极的气体供给口的前表面，使等离子体产生用气体通过三维网络结构中不规则形成的孔部。 因此，供给气体的分布均匀，以防止异常放电，从而可以进行不变化的均匀蚀刻。

公开(公告)号：US20060024924A1

公开(公告)日：2006-02-02

申请号：US11193487

申请日：2005-08-01

申请人： Hiroshi Haji ,  Kiyoshi Arita ,  Teruaki Nishinaka

发明人： Hiroshi Haji ,  Kiyoshi Arita ,  Teruaki Nishinaka

IPC分类号： H01L21/78 ,  H01L21/50

CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.