公开(公告)号：US06693789B2

公开(公告)日：2004-02-17

申请号：US09825860

申请日：2001-04-03

申请人： Hiroshi Inazumachi ,  Takeshi Ootsuka ,  Takeshi Kawase

发明人： Hiroshi Inazumachi ,  Takeshi Ootsuka ,  Takeshi Kawase

IPC分类号： H02N1300

CPC分类号： H01L21/6835 ,  Y10T29/49124

摘要： A built-in electrode type susceptor having excellent corrosion resistance and plasma resistance is obtained. A placement plate and a support plate made of ceramics are prepared, fixation holes are formed in this support plate, and feeding terminals consisting of a conductive composite ceramics are fitted into these fixation holes so as to penetrate through the support plate. A conductive material layer consisting of a conductive composite ceramics is formed on this support plate so as to come into contact with the feeding terminals, and the support plate and the placement plate are overlapped on each other via the conductive material layer on the support plate, and subjected to sintering and heat treatment under application of pressure, to thereby integrate these plates. Also, the conductive material layer is used as an internal electrode consisting of a conductive composite ceramics sintered body, to thereby obtain a built-in electrode type susceptor. At the time of overlapping and bonding the placement plate and the support plate, these may be bonded via a nonconductive layer having the same material as these plates.

摘要翻译： 获得具有优异的耐腐蚀性和等离子体电阻的内置电极型基座。 准备了由陶瓷制成的放置板和支撑板，在该支撑板上形成固定孔，将由导电性复合陶瓷构成的馈电端子嵌入到这些固定孔内，从而穿过支撑板。 在该支撑板上形成由导电性复合陶瓷构成的导电性材料层，以与馈电端子接触，支撑板和配置板通过支撑板上的导电材料层彼此重叠， 并在施加压力下进行烧结和热处理，从而使这些板结合。 此外，导电材料层用作由导电复合陶瓷烧结体组成的内部电极，从而获得内置的电极型基座。 在重叠和接合放置板和支撑板时，它们可以通过与这些板具有相同材料的非导电层接合。

公开(公告)号：US07512816B2

公开(公告)日：2009-03-31

申请号：US10580199

申请日：2004-11-19

申请人： Takeshi Ootsuka ,  Hideaki Yamashita ,  Haruo Ohta

发明人： Takeshi Ootsuka ,  Hideaki Yamashita ,  Haruo Ohta

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F9/00

CPC分类号： G06F3/061 ,  G06F1/3225 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0679 ,  H04N5/77 ,  H04N5/772 ,  H04N5/907 ,  H04N9/8042 ,  H04N9/8047 ,  Y02D10/154

摘要： In a recording device having one or more semiconductor memories mounted thereon, the number of semiconductor memories operating in parallel is restricted according to an available supply current of an accessing apparatus to which the recording device is attached.

摘要翻译： 在其中安装有一个或多个半导体存储器的记录装置中，并行操作的半导体存储器的数量根据附着有记录装置的访问装置的可用供应电流而受到限制。

公开(公告)号：US20070168881A1

公开(公告)日：2007-07-19

申请号：US11681427

申请日：2007-03-02

申请人： Koichi Nagoshi ,  Takayuki Fukushima ,  Ikuo Yoshida ,  Takeshi Ootsuka ,  Kiyohiko Honda

发明人： Koichi Nagoshi ,  Takayuki Fukushima ,  Ikuo Yoshida ,  Takeshi Ootsuka ,  Kiyohiko Honda

IPC分类号： G06F3/048

CPC分类号： G06F16/84

摘要： A distribution server and includes a communicator that communicates with multifunction apparatuses via a network a menu generator that generates menu information based on information obtained by the communicator, the information including display capability information and job capability information for each multifunction apparatus. The menu information includes information for execution of a job and a menu name assigned for the job. A data memory stores the generated menu information and a distributor retrieves, from the data memory, menu information requested by the multifunction apparatus and distributes, via the network, the menu information to the requesting multifunction apparatus.

摘要翻译： 一种分发服务器，包括通过网络与多功能设备通信的通信器，基于由通信器获得的信息生成菜单信息的菜单生成器，包括每个多功能设备的显示能力信息和作业能力信息的信息。 菜单信息包括用于执行作业的信息和为作业分配的菜单名称。 数据存储器存储生成的菜单信息，并且分发器从数据存储器检索由多功能设备请求的菜单信息，并经由网络将菜单信息分发给请求的多功能设备。

公开(公告)号：US08533559B2

公开(公告)日：2013-09-10

申请号：US12988660

申请日：2009-04-20

申请人： Takeshi Ootsuka

发明人： Takeshi Ootsuka

IPC分类号： H03M13/00

CPC分类号： G06F11/1048

摘要： An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface. A data distributor distributes (N+M) words to the respective (N+M) physical blocks to record by A words. In a case where a writing error has occurred, data recorded in a cell sharing page of the page and in a page of another physical block configuring the error correction code is read. A disappearing correction is carried out to the data of the cell sharing page by using the data, and thus the data of the cell sharing page is recovered and written. In this manner, in the multi-level nonvolatile memory, an error in writing of a certain page can be prevented from propagating to a written page sharing a cell.

摘要翻译： 通过将M字（M是自然数）的ECC奇偶校验相对于（A * N）个字的数据（A * N）字（A * N））的A字提取的N个字添加到（N + M）个字的纠错码 A和N是自然数）。 数据分配器将（N + M）个字分配到各个（N + M）个物理块以通过A字记录。 在发生写入错误的情况下，读取记录在页面的单元共享页面和配置纠错码的另一个物理块的页面中的数据。 通过使用数据对小区共享页面的数据进行消失校正，从而恢复和写入小区共享页面的数据。 以这种方式，在多级非易失性存储器中，可以防止某个页面的写入错误传播到共享单元的书写页面。

公开(公告)号：US20100293322A1

公开(公告)日：2010-11-18

申请号：US12812238

申请日：2008-10-06

申请人： Takeshi Ootsuka

发明人： Takeshi Ootsuka

IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7201 ,  G11C8/06

摘要： A semiconductor recording apparatus includes a logical-to-physical conversion table 115 showing correspondence between a physical address of said semiconductor memory and a logical address and writes the table to a flash memory 120. On receiving a write command issued from a host device 200, a block management section 114 selects a physical block with reference to said logical-to-physical conversion table, and updates said logical-to-physical conversion table. A logical-to-physical conversion table initializing section 117 updates a physical address corresponding to each logical address of the logical-to-physical conversion table into an invalid address. Accordingly the apparatus can render the number of rewrites of physical blocks uniform irrespective of writing conditions.

摘要翻译： 半导体记录装置包括表示所述半导体存储器的物理地址与逻辑地址之间的对应关系的逻辑到物理转换表115，并将该表写入闪速存储器120.在接收到从主机设备200发出的写命令时， 块管理部分114参考所述逻辑到物理转换表选择物理块，并更新所述逻辑到物理转换表。 逻辑到物理转换表初始化部分117将对应于逻辑到物理转换表的每个逻辑地址的物理地址更新成无效地址。 因此，无论写入条件如何，该装置可以使物理块的重写数量均匀化。

公开(公告)号：US20070204077A1

公开(公告)日：2007-08-30

申请号：US11663768

申请日：2005-09-29

申请人： Takeshi Ootsuka ,  Seigo Fujiwara

发明人： Takeshi Ootsuka ,  Seigo Fujiwara

IPC分类号： G06F13/00 ,  G06F12/00

CPC分类号： G06F13/405

摘要： A memory card controller for controlling data transfer between a host device that requests data transfer by issuing a command specifying a data amount and a memory card that executes a transfer operation from receipt of a transfer start instruction until receipt of a transfer end instruction. The memory card controller is provided with a clock start/end control unit 10 that suspends supply of a clock signal to the memory card when a data amount transferred from the memory card as a result of the transfer operation reaches a data amount specified by an nth command received from the host device, and resumes supply of the clock signal to the memory card if a subsequent command received with supply of the clock signal to the SD card in a suspended state specifies an address consecutive to an end address of data transfer requested by the nth command as a start address.

摘要翻译： 一种存储卡控制器，用于通过发出指定数据量的命令来请求数据传送的主机设备和从接收到传送开始指令直到接收传送结束指令之后执行传送操作的存储卡之间的数据传输。 存储卡控制器设置有时钟开始/结束控制单元10，当作为转移操作的结果从存储卡传送的数据量达到由第n个指定的数据量时，暂停向存储卡提供时钟信号 如果通过以暂停状态向SD卡提供时钟信号而接收的后续命令指定了与由所请求的数据传送的结束地址连续的地址，则从主机装置接收到的命令，并且恢复向存储卡提供时钟信号 第n个命令作为起始地址。

公开(公告)号：US08352807B2

公开(公告)日：2013-01-08

申请号：US12652790

申请日：2010-01-06

申请人： Hideaki Yamashita ,  Takeshi Ootsuka

发明人： Hideaki Yamashita ,  Takeshi Ootsuka

IPC分类号： G06F11/00

CPC分类号： G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7202

摘要： A host device 200A includes a data buffer 250. When data has been already written to a part of a physical block and data is additionally written to the physical block, it is determined whether or not the data written to the physical block is held in the data buffer. When the data is held, data is written to the block, and when an error exists, data in unit of physical blocks is rewritten. When the data is not held in the data buffer, a new physical block is required to be secured and then, data is written to the new block. Thereby, even when power is shut off or an error occurs during writing in the semiconductor memory device, destruction of data already written is prevented.

摘要翻译： 主机设备200A包括数据缓冲器250.当数据已被写入物理块的一部分并且数据被附加地写入物理块时，确定写入物理块的数据是否被保存在 数据缓冲区。 当数据保持时，将数据写入块，当存在错误时，重写物理块单位的数据。 当数据不保存在数据缓冲器中时，需要新的物理块来保护数据，然后将数据写入新的块。 因此，即使当在半导体存储器件中写入期间断电或出现错误时，也可以防止已经写入的数据的破坏。

公开(公告)号：US20110041036A1

公开(公告)日：2011-02-17

申请号：US12988660

申请日：2009-04-20

申请人： Takeshi Ootsuka

发明人： Takeshi Ootsuka

IPC分类号： G06F11/08

CPC分类号： G06F11/1048

摘要： An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface 1. A data distributor 3 distributes (N+M) words to the respective (N+M) physical blocks to record by A words. In a case where a writing error has occurred, data recorded in a cell sharing page of the page and in a page of another physical block configuring the error correction code is read. A disappearing correction is carried out to the data of the cell sharing page by using the data, and thus the data of the cell sharing page is recovered and written. In this manner, in the multi-level nonvolatile memory, an error in writing of a certain page can be prevented from propagating to a written page sharing a cell.

摘要翻译： 通过将M字（M是自然数）的ECC奇偶校验相对于（A * N）个字的数据（A * N）字（A * N））的A字提取的N个字添加到（N + M）个字的纠错码 A和N是自然数）。数据分配器3将（N + M）个字分配到各个（N + M）个物理块以通过A字记录。 在发生写入错误的情况下，读取记录在页面的单元共享页面和配置纠错码的另一个物理块的页面中的数据。 通过使用数据对小区共享页面的数据进行消失校正，从而恢复和写入小区共享页面的数据。 以这种方式，在多级非易失性存储器中，可以防止某个页面的写入错误传播到共享单元的书写页面。

公开(公告)号：US07175714B2

公开(公告)日：2007-02-13

申请号：US10613574

申请日：2003-07-03

申请人： Takeshi Ootsuka ,  Kazunori Endou

发明人： Takeshi Ootsuka ,  Kazunori Endou

IPC分类号： H01L29/06 ,  H01L21/00

CPC分类号： H01J37/32009 ,  C23C16/4581 ,  H01J37/3255

摘要： An electrode-built-in susceptor comprises a mounting plate and a supporting plate which are made of an aluminium-nitride-group-sintered member, an inner electrode which is made of a conductive aluminium-nitride-tantalum-nitride-composite-sintered-member or a conductive aluminium-nitride-tungsten-composite-sintered-member so as to be formed between the mounting plate and the supporting plate, power supplying terminals 16, 16 which is disposed in fixing holes 13, 13 which are formed on the supporting plate so as to be attached to the inner electrode. The power supplying terminals are made of a conductive aluminium-nitride-tantalum-nitride-composite-sintered-member.By doing this, it is possible to provide an electrode-built-in susceptor which has superior durability under a high temperature oxidizing atmosphere condition and a method for manufacturing an electrode-built-in susceptor with a high product yield and a low production cost.

摘要翻译： 电极内置基座包括由氮化铝基烧结构件制成的安装板和支撑板，由导电氮化铝 - 氮化钽 - 复合烧结构件制成的内部电极， 构件或导电性氮化铝 - 钨复合烧结构件，以形成在安装板和支撑板之间;供电端子16,16，其设置在形成在支撑件上的固定孔13,13中; 板，以便附接到内电极。 供电端子由导电氮化铝 - 氮化钽 - 复合烧结构件制成。 通过这样做，可以提供一种在高温氧化气氛条件下具有优异的耐久性的电极内置基座，以及具有高产品收率和低生产成本的电极内置基座的制造方法。

公开(公告)号：US5587807A

公开(公告)日：1996-12-24

申请号：US317793

申请日：1994-10-04

申请人： Takeshi Ootsuka ,  Masaaki Higashida

发明人： Takeshi Ootsuka ,  Masaaki Higashida

IPC分类号： H04N5/92 ,  G11B20/12 ,  G11B20/18 ,  H04N5/926 ,  H04N5/94 ,  H04N5/76

CPC分类号： H04N5/9261 ,  G11B20/1809 ,  G11B20/1876 ,  H04N5/94

摘要： In an apparatus for processing input N-bit digital video data with an error correction parity, the input N-bit digital video data includes each one sample of higher-order-N-bit data and a plurality of samples of lower-order-(M-N)-bit data, wherein M>N. An error correction circuit corrects an error of input N-bit digital video data, outputs error-corrected N-bit digital video data, and generates an error detection signal representing an error which can not be corrected. Further, a data combining circuit converts the error-corrected N-bit digital video data into M-bit digital video data, and an error classifying circuit classifies the error detection signal into a first error detection signal representing an error of the each one sample of the higher-order-N-bit data and a second error detection signal representing an error of the plurality of samples of the lower-order-(M-N)-bit data. An error concealment circuit performs an error concealment process for the converted M-bit digital video data based on only the first error detection signal.

摘要翻译： 在用于处理具有纠错奇偶校验的输入N位数字视频数据的装置中，输入的N位数字视频数据包括高阶N位数据的每一个采样和低阶N位数据的多个采样 MN）位数据，其中M> N。 错误校正电路校正输入的N位数字视频数据的误差，输出经纠错的N位数字视频数据，并产生表示无法校正的错误的错误检测信号。 此外，数据组合电路将经纠错的N位数字视频数据转换为M位数字视频数据，误差分类电路将误差检测信号分类为表示每个样本的误差的第一错误检测信号 高位N位数据和表示低阶（MN）位数据的多个样本的误差的第二错误检测信号。 错误隐藏电路仅对第一错误检测信号进行转换的M位数字视频数据的错误隐藏处理。