公开(公告)号：US07177188B2

公开(公告)日：2007-02-13

申请号：US10775254

申请日：2004-02-11

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Yoshifumi Yaoi ,  Yasuaki Iwase ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Kenichi Tanaka

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Yoshifumi Yaoi ,  Yasuaki Iwase ,  Masaru Nawaki ,  Yoshinao Morikawa ,  Kenichi Tanaka

IPC分类号： G11C16/00

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  H01L21/28282 ,  H01L29/7923

摘要： A semiconductor memory device includes: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

摘要翻译： 半导体存储器件包括：存储单元，具有通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧的扩散区域，并具有相反的导电类型 形成在栅电极的两侧并具有保持电荷的功能的存储器功能单元; 以及放大器，存储单元和放大器彼此连接，使得存储单元的输出被输入到放大器。

公开(公告)号：US07170791B2

公开(公告)日：2007-01-30

申请号：US10848236

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/06

CPC分类号： H01L29/66825 ,  G11C11/22 ,  G11C16/0475 ,  G11C16/3454 ,  G11C16/3459 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887

摘要： A programming verification method of verifying programming of a nonvolatile memory cell, the method comprising at least the steps of: selecting first, second, . . . and n-th references corresponding to first, second, . . . and n-th threshold voltages specifying lower limit values of states 1, 2, . . . and n, respectively; applying a programming voltage to the nonvolatile memory cell; sensing a threshold voltage level of the nonvolatile memory cell; comparing the sensed threshold voltage level with the first reference to output a first result; comparing the threshold voltage level with one of the second and third references selected according to the first result to output a second result; and comparing the first and second results with an expectation value and, in the case where the first and second results are equal to the expectation value, indicating that the programming has succeeded, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 一种验证非易失性存储单元的编程的编程验证方法，所述方法至少包括以下步骤：选择第一，第二， 。 。 和对应于第一，第二的第n个引用。 。 。 和指定状态1,2的下限值的第n阈值电压。 。 。 和n; 向非易失性存储单元施加编程电压; 感测所述非易失性存储单元的阈值电压电平; 将感测到的阈值电压电平与第一参考值进行比较以输出第一结果; 将阈值电压电平与根据第一结果选择的第二和第三参考中的一个进行比较以输出第二结果; 以及将所述第一和第二结果与期望值进行比较，并且在所述第一和第二结果等于期望值的情况下，指示所述编程已成功，其中所述非易失性存储单元包括形成在半导体层上的栅电极 通过栅极绝缘膜，设置在栅极电极下方的沟道区域，作为扩散区域的源极和漏极，设置在沟道区域的两侧并且具有与沟道区域的导电类型相反的导电类型，以及存储功能单元 栅电极的两侧并具有保持电荷的功能。

公开(公告)号：US07102941B2

公开(公告)日：2006-09-05

申请号：US10847625

申请日：2004-05-18

申请人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Masaru Nawaki ,  Yasuaki Iwase ,  Yoshinao Morikawa

发明人： Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Masaru Nawaki ,  Yasuaki Iwase ,  Yoshinao Morikawa

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C16/0475 ,  G11C29/78

摘要： A semiconductor memory device including (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundant block; and (C) a circuit for making the decoder of the defective block unusable and, only when the defective block is addressed, for making the decoder of the redundant block usable.

摘要翻译： 一种半导体存储器件，包括（A）全局线; （B）具有（i）本地线的存储器阵列，（ii）连接到全局线和本地线的解码器，以及（iii）由多个存储器单元构成的存储器块和冗余块，每个存储器单元和 通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧并且具有与沟道区域相反的导电类型的扩散区域;以及存储器 功能单元形成在栅电极的两侧并且具有保持电荷的功能，该存储器阵列具有当解码器可用时的功能，全局线根据地址信息有选择地连接到一条局部线路， 当存储块中包含有缺陷块并且解码器不可用时，本地线与全局线分离，并且用冗余块替换缺陷块; 以及（C）用于使缺陷块的解码器不可用的电路，并且仅当寻址缺陷块时，才能使冗余块的解码器可用。

公开(公告)号：US20050002263A1

公开(公告)日：2005-01-06

申请号：US10848082

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/02 ,  G11C16/24 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/24

摘要： A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.

摘要翻译： 一种向非易失性半导体存储装置提供高速写入的写入控制系统，包括：（a）多个存储元件，每个存储元件具有：设置在具有中间栅极绝缘膜的半导体层上的栅电极; 设置在栅电极下方的沟道区; 扩散区，设置在沟道区的两侧，具有与沟道区相反的极性; 以及设置在栅电极的两侧上的具有保持电荷功能的存储器功能部件，（b）包括页缓冲电路的存储器阵列，（c）CPU控制对存储器阵列的写入。 CPU用第一个数据字节加载页面缓冲电路的第一个平面，并用第一个平面中存储的数据的第一个字节进行写入。 此外，CPU将第二字节的数据写入第二平面，并且将已经存储在第一平面中的数据的第一字节写入存储器阵列中，将已经存储在第二平面中的数据的第二字节写入。

公开(公告)号：US20050002258A1

公开(公告)日：2005-01-06

申请号：US10848312

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G06F12/14 ,  G06F21/02 ,  G11C7/24 ,  G11C16/02 ,  G11C16/04 ,  G11C16/22 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  G11C7/24 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/22 ,  G11C2216/06 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42384 ,  H01L29/792

摘要： There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

摘要翻译： 提供了一种包括易于小型化的非易失性存储元件的半导体存储装置和便携式电子设备。 半导体存储装置包括其中布置有多个存储元件1的存储单元阵列21和写状态机32.存储元件1包括经由栅极绝缘体103形成在半导体层102上的栅电极104，沟道 布置在栅电极104下方的区域，扩散区域107a，107b，其位于沟道区域的两侧，并且具有与沟道区域相反的导电类型和位于栅电极两侧的存储器功能体109 并且具有保持电荷的功能。 写状态机32可以选择性地防止在预定范围内的存储器元件中的数据的编程和擦除。

公开(公告)号：US07405974B2

公开(公告)日：2008-07-29

申请号：US10848324

申请日：2004-05-19

申请人： Yoshifumi Yaoi ,  Yasuaki Iwase ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yoshifumi Yaoi ,  Yasuaki Iwase ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/00

CPC分类号： G11C16/10 ,  G11C7/10 ,  G11C7/1039 ,  G11C2207/2245

摘要： A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

摘要翻译： 半导体存储器件包括页缓冲电路和存储元件的布置，每个存储元件包括：设置在具有中间栅极绝缘膜的半导体层上的栅电极; 设置在栅电极下方的沟道区; 扩散区，设置在沟道区的两侧，具有与沟道区相反的极性; 以及设置在栅电极两侧的具有存储电荷功能的记忆功能部件。 页面缓冲电路提供了在存储器阵列控制器和用户之间共享的公共资源。 页面缓冲电路具有包含随机存取存储器阵列的两个平面。 页面缓冲电路还包括模式控制部分，以便以用户模式访问主总线上的平面并且以存储器控制模式通过存储器阵列控制器访问平面。

公开(公告)号：US07050337B2

公开(公告)日：2006-05-23

申请号：US10848082

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C7/00

CPC分类号： G11C16/24

摘要： A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.

摘要翻译： 一种向非易失性半导体存储装置提供高速写入的写入控制系统，包括：（a）多个存储元件，每个存储元件具有：设置在具有中间栅极绝缘膜的半导体层上的栅电极; 设置在栅电极下方的沟道区; 扩散区，设置在沟道区的两侧，具有与沟道区相反的极性; 以及设置在栅电极两侧的具有保持电荷功能的存储器功能部件，（b）包括页缓冲电路的存储器阵列，（c）CPU控制对存储器阵列的写入。 CPU用第一个数据字节加载页面缓冲电路的第一个平面，并用第一个平面中存储的数据的第一个字节进行写入。 此外，CPU将第二字节的数据写入第二平面，并且将已经存储在第一平面中的数据的第一字节写入存储器阵列中，将已经存储在第二平面中的数据的第二字节写入。

公开(公告)号：US06992933B2

公开(公告)日：2006-01-31

申请号：US10848614

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C11/34

CPC分类号： H01L29/66825 ,  G11C11/22 ,  G11C16/0475 ,  G11C16/3431 ,  G11C16/3454 ,  G11C16/3459 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66833 ,  H01L29/7887

摘要： A method of verifying programming of a nonvolatile memory cell to a desired state, the method comprising the steps of: selecting first and second references respectively corresponding to first and second voltages; applying a programming voltage to the memory cell; sensing a threshold voltage level of the memory cell; and comparing the sensed threshold voltage level with the first and second references and, in the case where the threshold voltage level is higher than the first reference and lower than the second reference, indicating that the memory cell is programmed into the desired state, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region formed below the gate electrode, a source and a drain as diffusion regions formed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.

摘要翻译： 一种将非易失性存储单元的编程验证为期望状态的方法，所述方法包括以下步骤：分别对应于第一和第二电压选择第一和第二参考; 将编程电压施加到所述存储器单元; 感测存储器单元的阈值电压电平; 以及将感测的阈值电压电平与第一和第二参考值进行比较，并且在阈值电压电平高于第一参考值且低于第二参考值的情况下，指示存储器单元被编程到期望状态，其中 非易失性存储单元包括通过栅极绝缘膜形成在半导体层上的栅极电极，形成在栅极电极下方的沟道区域，作为在沟道区域的两侧形成的扩散区域的源极和漏极，并且具有与 沟道区域以及形成在栅电极的两侧上并具有保持电荷功能的存储功能单元。

公开(公告)号：US07315603B2

公开(公告)日：2008-01-01

申请号：US10848312

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C8/00

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  G11C7/24 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/22 ,  G11C2216/06 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42384 ,  H01L29/792

摘要： There is provided a semiconductor storage device and portable electronic equipment including a nonvolatile memory element that can easily be miniaturized. The semiconductor storage device includes a memory cell array 21 in which a plurality of memory elements 1 are arranged and a write state machine 32. The memory element 1 includes a gate electrode 104 formed on a semiconductor layer 102 via a gate insulator 103, a channel region arranged below the gate electrode 104, diffusion regions 107a, 107b that are located on both sides of the channel region and have a conductive type opposite to that of the channel region and memory function bodies 109 that are located on both sides of the gate electrode 104 and have a function to retain electric charge. The write state machine 32 can selectively prevent program and erase of data in the memory elements within a predetermined range.

摘要翻译： 提供了一种包括易于小型化的非易失性存储元件的半导体存储装置和便携式电子设备。 半导体存储装置包括其中布置有多个存储元件1的存储单元阵列21和写入状态机32。 存储元件1包括通过栅极绝缘体103形成在半导体层102上的栅电极104，布置在栅电极104下方的沟道区，位于沟道区两侧的扩散区107a，107b，并具有 与沟道区域和记忆功能体109相对的导电类型，其位于栅极电极104的两侧并具有保持电荷的功能。 写状态机32可以选择性地防止在预定范围内的存储器元件中的数据的编程和擦除。

公开(公告)号：US06992926B2

公开(公告)日：2006-01-31

申请号：US10848605

申请日：2004-05-19

申请人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

发明人： Yasuaki Iwase ,  Yoshifumi Yaoi ,  Hiroshi Iwata ,  Akihide Shibata ,  Yoshinao Morikawa ,  Masaru Nawaki

IPC分类号： G11C16/06

CPC分类号： H01L21/28282 ,  G11C16/08 ,  H01L29/792

摘要： A semiconductor storage device is provided with a gate electrode, a semiconductor layer, a gate insulating film sandwiched between the gate electrode and the semiconductor layer, a channel region under the gate electrode, diffusion regions provided respectively on two sides of the channel regions and being of the other conductivity region than the channel region, memory elements 1 provided respectively on two sides of the gate electrode and having a function of holding charges, and a word line driver circuit, in which the CMOS technique is used. The driver circuit includes a common node for supplying a potential for activating an output inverter for driving a row word line. While the semiconductor storage device is in a read mode, a CMOS inverter other than the output inverter controls a signal at the common node, the CMOS inverter connected to a read input line. While the semiconductor storage device is in writing/erasing mode, a plurality of writing/erasing transistors connected in series to the node are activated in accordance with an address signal, in order to lower the common node to a low potential.

摘要翻译： 半导体存储装置设置有栅电极，半导体层，夹在栅极电极和半导体层之间的栅极绝缘膜，栅电极下方的沟道区域，分别设置在沟道区域的两侧的扩散区域， 的另一个导电区域，分别设置在栅电极的两侧并具有保持电荷的功能的存储元件1和使用CMOS技术的字线驱动电路。 驱动器电路包括用于提供用于激活用于驱动行字线的输出反相器的电位的公共节点。 当半导体存储装置处于读取模式时，除了输出反相器之外的CMOS反相器控制公共节点处的信号，CMOS反相器连接到读取输入线。 当半导体存储装置处于写入/擦除模式时，根据地址信号激活与该节点串联连接的多个写/擦除晶体管，以便将公共节点降低到低电位。