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    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07800155B2

    公开(公告)日：2010-09-21

    申请号：US11858585

    申请日：2007-09-20

    申请人： Koichi Matsuno

    发明人： Koichi Matsuno

    IPC分类号： H01L27/115

    CPC分类号： H01L27/115 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the gate insulating film, a second gate electrode formed on the gate insulating film between the first gate electrode and a contact plug, a first silicon oxide film formed above the substrate between the first and second gate electrodes, a first silicon nitride film formed along the substrate and a side surface of the second gate electrode between the contact plug and the second gate electrode, a second silicon oxide film formed on the first silicon oxide film, the first gate electrode and the second gate electrode, the second silicon oxide film including an upper surface having a height greater than the height of a first upper surface of the first gate electrode relative to the substrate, and a second silicon nitride film formed on the second silicon oxide film.

    摘要翻译： 半导体器件包括形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的第一栅电极，形成在第一栅电极和接触插塞之间的栅极绝缘膜上的第二栅电极，第一氧化硅膜 形成在第一和第二栅电极之间的衬底上方，沿着衬底形成的第一氮化硅膜和在接触插塞和第二栅电极之间的第二栅电极的侧表面，形成在第一硅上的第二氧化硅膜 氧化膜，第一栅电极和第二栅电极，第二氧化硅膜包括具有比第一栅电极的第一上表面相对于衬底的高度高的上表面，以及第二氮化硅膜 形成在第二氧化硅膜上。

    Method of controlling a communication terminal having a plurality of functions, communication terminal apparatus, communication control system
    5.
    发明授权
    Method of controlling a communication terminal having a plurality of functions, communication terminal apparatus, communication control system 有权
    控制具有多种功能的通信终端的方法，通信终端装置，通信控制系统

    公开(公告)号：US07162240B2

    公开(公告)日：2007-01-09

    申请号：US11084891

    申请日：2005-03-21

    申请人： Shinji Okazaki ,  Hirokazu Takagaki ,  Katsumi Hirota ,  Koichi Matsuno ,  Ichiro Hino

    发明人： Shinji Okazaki ,  Hirokazu Takagaki ,  Katsumi Hirota ,  Koichi Matsuno ,  Ichiro Hino

    IPC分类号： H04Q7/20 ,  H04Q7/36

    CPC分类号： H04M15/47 ,  H04M1/6041 ,  H04M1/67 ,  H04M1/72519 ,  H04M1/72522 ,  H04M1/72558 ,  H04M2215/0148 ,  H04W52/0264

    摘要： When a radio communication is made between a predetermined base station and a communication terminal, the communication terminal is allowed to make a communication if a predetermined registration processing is made. If the above registration processing is not executed, then predetermined functions other than a communication function of the communication terminal are limited. Moreover, when a predetermined operation mode is set by an operation means, at least a transmission processing at a radio communication means is stopped and an execution of predetermined functions other than the radio communication processing is not restricted. Thus, when a communication terminal apparatus incorporates therein other functions than an audio reproducing function, operation of such function can be limited properly. Moreover, when other functions such as an audio reproducing function are incorporated into a communication terminal apparatus, operations of the functions thus incorporated can be limited properly and the communication functions can be stopped properly.

    摘要翻译： 当在预定基站和通信终端之间进行无线电通信时，如果进行了预定的登记处理，则通信终端被允许进行通信。 如果不执行上述注册处理，则限制通信终端的通信功能以外的预定功能。 此外，当通过操作装置设定预定操作模式时，至少停止在无线电通信装置处的发送处理，并且不限制除了无线电通信处理之外的预定功能的执行。 因此，当通信终端装置在其中并入具有比音频再现功能的其它功能时，可以适当地限制这种功能的操作。 此外，当诸如音频再现功能的其它功能被并入到通信终端设备中时，可以适当地限制所包含的功能的操作，并且可以适当地停止通信功能。

    Semiconductor memory device with selective gate transistor
    6.
    发明授权
    Semiconductor memory device with selective gate transistor 失效
    具有选择栅极晶体管的半导体存储器件

    公开(公告)号：US07795668B2

    公开(公告)日：2010-09-14

    申请号：US11772446

    申请日：2007-07-02

    申请人： Koichi Matsuno

    发明人： Koichi Matsuno

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521

    摘要： A semiconductor device includes a pair of selective gate lines formed above a semiconductor substrate, plural word lines formed above the substrate, plural contact plugs located between the selective gate lines, a first insulator formed in the trenches between the word lines, the first insulator including a first insulating film having a first upper surface flush with the substrate surface, a second insulator formed in the trenches between the contact plugs and including second and third insulating films, and a boro-phosphor-silicate glass film formed on the third insulating film and between the contact plugs. The second insulating film is of a kind same as the first insulating film. The third insulating film has a higher resistance to a wet etching process than the second insulating film. An interface between the second and third insulating films is located between a bottom and an upper end of the trench.

    摘要翻译： 半导体器件包括形成在半导体衬底上的一对选择栅极线，形成在衬底上的多个字线，位于选择栅极线之间的多个接触插塞，形成在字线之间的沟槽中的第一绝缘体，第一绝缘体包括 具有与基板表面齐平的第一上表面的第一绝缘膜，形成在接触插塞之间的沟槽中并包括第二和第三绝缘膜的第二绝缘体和形成在第三绝缘膜上的硼硅酸盐玻璃膜，以及 在接触塞之间。 第二绝缘膜与第一绝缘膜相同。 第三绝缘膜比第二绝缘膜具有比湿蚀刻工艺更高的耐受性。 第二和第三绝缘膜之间的界面位于沟槽的底端和上端之间。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20080251883A1

    公开(公告)日：2008-10-16

    申请号：US12142869

    申请日：2008-06-20

    申请人： Yoshinori KITAMURA ,  Koichi Matsuno ,  Kazunori Nishikawa

    发明人： Yoshinori KITAMURA ,  Koichi Matsuno ,  Kazunori Nishikawa

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7881 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541 ,  H01L29/66825

    摘要： A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively.

    摘要翻译： 一种半导体器件包括形成有多个具有第一开口宽度的第一元件隔离沟槽和具有比第一开口宽度更大的开口宽度的多个第二元件隔离沟槽的半导体衬底，埋在第一元件隔离沟槽中的元件隔离绝缘膜 使得沟槽的上部分别具有部分开口并分别埋在第二元件隔离沟槽中，并且分别形成为填充第一元件隔离沟槽的开口的涂覆型氧化物膜。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20080246075A1

    公开(公告)日：2008-10-09

    申请号：US11858585

    申请日：2007-09-20

    申请人： Koichi Matsuno

    发明人： Koichi Matsuno

    IPC分类号： H01L29/00 ,  H01L21/3205

    CPC分类号： H01L27/115 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/11521 ,  H01L27/11524 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate electrodes for a plurality of memory cell transistors on a surface of a semiconductor substrate, each gate electrode including a polycrystalline layer on an upper portion thereof; filling a first silicon oxide film between the plurality of gate electrodes; exposing the polycrystalline layers; depositing a metal layer on the polycrystalline layers; alloying the metal layer with the polycrystalline layers to form silicide layers and removing a remainder metal layer unused as the silicide layer; forming a second silicon oxide film on and between the gate electrodes, an upper surface of the second silicon oxide film being higher than an upper surface of the gate electrode in regions over the gate electrodes and regions between the gate electrodes; and forming a silicon nitride film on the second silicon oxide film.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底的表面上形成用于多个存储单元晶体管的多个栅电极，每个栅电极在其上部包括多晶层; 在所述多个栅电极之间填充第一氧化硅膜; 暴露多晶层; 在多晶层上沉积金属层; 将金属层与多晶层合金化以形成硅化物层并除去未被用作硅化物层的剩余金属层; 在所述栅电极之间和之间形成第二氧化硅膜，所述第二氧化硅膜的上表面高于所述栅极电极和所述栅电极之间的区域中的所述栅电极的上表面; 以及在所述第二氧化硅膜上形成氮化硅膜。

    Semiconductor device and method of manufacturing the same
    9.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07402499B2

    公开(公告)日：2008-07-22

    申请号：US11445373

    申请日：2006-06-02

    申请人： Yoshinori Kitamura ,  Koichi Matsuno ,  Kazunori Nishikawa

    发明人： Yoshinori Kitamura ,  Koichi Matsuno ,  Kazunori Nishikawa

    IPC分类号： H01L21/76

    CPC分类号： H01L29/7881 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541 ,  H01L29/66825

    摘要： A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widths, element isolation insulating films buried in the first element isolation trenches so that upper parts of the trenches have partial openings, respectively and buried in the second element isolation trenches respectively, and coating type oxide films formed so as to fill the openings of the first element isolation trenches, respectively.

    摘要翻译： 一种半导体器件包括形成有多个具有第一开口宽度的第一元件隔离沟槽和具有比第一开口宽度更大的开口宽度的多个第二元件隔离沟槽的半导体衬底，埋在第一元件隔离沟槽中的元件隔离绝缘膜 使得沟槽的上部分别具有部分开口并分别埋在第二元件隔离沟槽中，并且分别形成为填充第一元件隔离沟槽的开口的涂覆型氧化物膜。

    Semiconductor device and method of manufacturing a semiconductor device
    10.
    发明授权
    Semiconductor device and method of manufacturing a semiconductor device 失效

    公开(公告)号：US07095093B2

    公开(公告)日：2006-08-22

    申请号：US10839140

    申请日：2004-05-06

    申请人： Tadashi Iguchi ,  Hiroaki Tsunoda ,  Koichi Matsuno

    发明人： Tadashi Iguchi ,  Hiroaki Tsunoda ,  Koichi Matsuno

    IPC分类号： H01L29/00

    CPC分类号： H01L21/28123 ,  H01L21/28247 ,  H01L21/76224 ,  H01L21/76232

    摘要： A semiconductor device comprises a semiconductor substrate having a substrate top surface on which a device should be formed; a gate electrode having an opposed surface opposed to said substrate top surface, and electrically insulated from said semiconductor substrate by a gate insulating film, a trench formed through said gate electrode into said semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of said substrate top surface, a first boundary end portion, which is defined between a substrate side surface of said semiconductor substrate forming a part of the side surface of said trench and said substrate top surface, and a second boundary end portion, which is defined between a gate side surface of said gate electrode forming another part of the side surface of said trench and said opposed surface, wherein said first boundary end portion and said second boundary end portion have spherical shapes having a curvature radius not smaller than 30 angstrom.