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    Semiconductor device with improved planarity and reduced parasitic capacitance
    1.
    发明授权
    Semiconductor device with improved planarity and reduced parasitic capacitance 有权
    具有改善的平面性和降低的寄生电容的半导体器件

    公开(公告)号：US06153918A

    公开(公告)日：2000-11-28

    申请号：US138017

    申请日：1998-08-21

    申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Keiichi Yamada ,  Keiichi Higashitani

    发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Keiichi Yamada ,  Keiichi Higashitani

    IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L29/00

    CPC分类号： H01L21/76237 ,  H01L21/823475

    摘要： In a semiconductor device and a method of manufacturing the same, a dummy region which can suppress occurrence of a parasitic capacity can be provided for reducing a difference in level without increasing manufacturing steps in number. A semiconductor substrate is provided at its main surface with an isolation region formed by a trench, and a dummy region leaving the main surface is formed in the isolation region for the purpose of reducing an influence by the difference in level in a later step. The dummy region includes p- and n-type impurity regions each extending a predetermined depth from the surface. Since a pn junction occurs at the bottom of the impurity region, a depletion layer spreads in the pn junction, and thereby reduces a parasitic capacity between the dummy region and a conductive interconnection located in a crossing direction at a higher position. The impurity regions and source/drain regions of p- and n-channel transistors in active regions are simultaneously formed by impurity implantation.

    摘要翻译： 在半导体器件及其制造方法中，可以提供能够抑制寄生电容的发生的虚拟区域，以减少水平差而不增加数量的制造步骤。 半导体衬底在其主表面上设置有由沟槽形成的隔离区域，并且在隔离区域中形成了离开主表面的虚拟区域，以便减少后续步骤中的电平差的影响。 虚拟区域包括各自从表面延伸预定深度的p型和n型杂质区。 由于在杂质区域的底部发生pn结，所以在pn结中扩散耗尽层，从而降低位于较高位置处的交叉方向上的虚设区域和导电配线之间的寄生电容。 有源区中的p沟道晶体管和n沟道晶体管的杂质区和源/漏区同时由杂质注入形成。

    Semiconductor device provided with a field-effect transistor and method of manufacturing the same
    3.
    发明授权
    Semiconductor device provided with a field-effect transistor and method of manufacturing the same 有权
    具有场效晶体管的半导体装置及其制造方法

    公开(公告)号：US06232640B1

    公开(公告)日：2001-05-15

    申请号：US09413513

    申请日：1999-10-06

    申请人： Masakazu Okada ,  Keiichi Higashitani

    发明人： Masakazu Okada ,  Keiichi Higashitani

    IPC分类号： H01L2972

    CPC分类号： H01L29/0847 ,  H01L21/823878 ,  H01L29/0657 ,  H01L29/41725 ,  H01L29/665

    摘要： A semiconductor device can reduce a leak current, and a manufacturing method can provide such a semiconductor device. A semiconductor device includes an isolating and insulating film formed on a main surface of a semiconductor substrate including a first conductivity type region, and also includes a field-effect transistor. The field-effect transistor includes a second conductivity type region neighboring to the isolating and insulating film, a gate electrode, a lower layer side wall film formed on a side surface of the gate electrode, an upper layer side wall film formed on the lower layer side wall film and containing a material different from that of the lower layer side wall film, and a high-melting-point metal silicide layer formed on the second conductivity type region. The upper surface of the isolating and insulating film is located at a level substantially equal to or lower than the main surface of the semiconductor substrate and higher than a junction boundary surface between the first and second conductivity type regions.

    摘要翻译： 半导体器件可以减少泄漏电流，并且制造方法可以提供这种半导体器件。一种半导体器件包括形成在包括第一导电类型区域的半导体衬底的主表面上的隔离和绝缘膜，并且还包括场 - 影响晶体管。 场效应晶体管包括与隔离绝缘膜相邻的第二导电类型区域，栅电极，形成在栅电极的侧表面上的下层侧壁膜，形成在下层上的上层侧壁膜 并且含有与下层侧壁膜不同的材料，以及形成在第二导电类型区域上的高熔点金属硅化物层。 隔离绝缘膜的上表面位于基本上等于或低于半导体衬底的主表面的水平面，并且高于第一和第二导电类型区域之间的结界面。

    Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby
    4.
    发明授权
    Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby 失效
    制造半导体器件的方法及其制造的半导体器件

    公开(公告)号：US06383910B2

    公开(公告)日：2002-05-07

    申请号：US09800579

    申请日：2001-03-08

    申请人： Masakazu Okada ,  Keiichi Higashitani ,  Hiroyuki Chibahara

    发明人： Masakazu Okada ,  Keiichi Higashitani ,  Hiroyuki Chibahara

    IPC分类号： H01L214763

    CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is described a method of manufacturing a semiconductor device which ensures formation of a step in an alignment mark, to thereby improve the accuracy of alignment. A tungsten layer is formed on an interlayer dielectric film including an opening for use in forming an alignment mark. The tungsten layer is abraded by means of the CMP technique. At this time, the initial thickness of the interlayer dielectric film is made greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion, thus ensuring formation of an alignment step. Further, a gate electrode is removed from the position where a contact alignment mark is formed. Alternatively, an aluminum electrode is removed from a position immediately below a through hole alignment mark.

    摘要翻译： 描述了制造半导体器件的方法，其确保对准标记中的台阶的形成，从而提高对准精度。 在包含用于形成对准标记的开口的层间电介质膜上形成钨层。 钨层通过CMP技术磨损。 此时，层间电介质膜的初始厚度大于可识别的对准的最小台阶和磨损量的总和，从而确保对准步骤的形成。 此外，从形成接触对准标记的位置去除栅电极。 或者，从通孔对准标记的正下方的位置除去铝电极。

    Semiconductor device with a first dummy pattern
    6.
    发明授权
    Semiconductor device with a first dummy pattern 有权
    具有虚拟图案的半导体器件

    公开(公告)号：US06753246B2

    公开(公告)日：2004-06-22

    申请号：US10419770

    申请日：2003-04-22

    申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

    发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

    IPC分类号： H01L214763

    CPC分类号： H01L21/31053 ,  H01L21/76229

    摘要： The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

    摘要翻译： 半导体器件包括半导体衬底，并且在半导体衬底中的元件隔离区域中具有间距小于第一A / A虚设图形的间距的第一有源区A / A虚拟图案和第二A / A虚拟图案 。 第一A / A虚拟图案的放置和第二A / A虚拟图案的放置在单独的步骤中进行。 半导体衬底可以被划分成多个网格区域，并且可以根据网格区域被位于其中的元素图案占据的区域而将虚设图案放置在每个网格区域中。

    Liquid crystal device having spacers and manufacturing method thereof
    10.
    发明授权
    Liquid crystal device having spacers and manufacturing method thereof 有权
    具有间隔物的液晶装置及其制造方法

    公开(公告)号：US06226067B1

    公开(公告)日：2001-05-01

    申请号：US09163846

    申请日：1998-09-30

    申请人： Kenji Nishiguchi ,  Masakazu Okada ,  Kiyofumi Hashimoto

    发明人： Kenji Nishiguchi ,  Masakazu Okada ,  Kiyofumi Hashimoto

    IPC分类号： G02F11339

    CPC分类号： G02F1/13394 ,  G02F1/13392

    摘要： Disclosed is a liquid crystal light modulating element comprising a pair of substrates and a liquid crystal modulating layer interposed between the substrates. The liquid crystal modulating layer mainly comprises (1) a liquid crystal material for light modulation, (2) a plurality of spacers for maintaining a gap between the substrates, and (3) a plurality of resin structural nodules for supporting and adhering said pair of substrates. The resin structural nodules are arranged within a light modulating region based on a predetermined principle or a predetermined pattern.

    摘要翻译： 公开了一种液晶光调制元件，其包括一对基板和插入在基板之间的液晶转换层。 液晶转换层主要包括（1）用于光调制的液晶材料，（2）多个用于保持基板之间的间隙的间隔物，（3）多个树脂结构结块，用于支撑和粘附所述一对 底物。 基于预定原理或预定图案将树脂结构结节布置在光调制区域内。