公开(公告)号：US06531737B2

公开(公告)日：2003-03-11

申请号：US09208477

申请日：1998-12-10

申请人： Masakazu Okada ,  Keiichi Higashitani ,  Hiroshi Kawashima

发明人： Masakazu Okada ,  Keiichi Higashitani ,  Hiroshi Kawashima

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon semiconductor substrate has a plurality of active regions having an impurity region and an isolating region which electrically isolates these active regions from each other. The isolating region is formed of a silicon nitride film. A contact hole penetrates an interlayer insulating film and reaches an impurity region. In this semiconductor device, when the contact hole falls across the impurity region and the isolating region, an amount of erosion in the isolating region is reduced.

摘要翻译： 硅半导体衬底具有多个具有杂质区域的有源区和将这些有源区彼此电隔离的隔离区。 隔离区由氮化硅膜形成。 接触孔穿透层间绝缘膜并到达杂质区域。 在该半导体装置中，当接触孔落在杂质区域和隔离区域时，隔离区域的侵蚀量降低。

公开(公告)号：US06153918A

公开(公告)日：2000-11-28

申请号：US138017

申请日：1998-08-21

申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Keiichi Yamada ,  Keiichi Higashitani

发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Keiichi Yamada ,  Keiichi Higashitani

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L29/00

CPC分类号： H01L21/76237 ,  H01L21/823475

摘要： In a semiconductor device and a method of manufacturing the same, a dummy region which can suppress occurrence of a parasitic capacity can be provided for reducing a difference in level without increasing manufacturing steps in number. A semiconductor substrate is provided at its main surface with an isolation region formed by a trench, and a dummy region leaving the main surface is formed in the isolation region for the purpose of reducing an influence by the difference in level in a later step. The dummy region includes p- and n-type impurity regions each extending a predetermined depth from the surface. Since a pn junction occurs at the bottom of the impurity region, a depletion layer spreads in the pn junction, and thereby reduces a parasitic capacity between the dummy region and a conductive interconnection located in a crossing direction at a higher position. The impurity regions and source/drain regions of p- and n-channel transistors in active regions are simultaneously formed by impurity implantation.

摘要翻译： 在半导体器件及其制造方法中，可以提供能够抑制寄生电容的发生的虚拟区域，以减少水平差而不增加数量的制造步骤。 半导体衬底在其主表面上设置有由沟槽形成的隔离区域，并且在隔离区域中形成了离开主表面的虚拟区域，以便减少后续步骤中的电平差的影响。 虚拟区域包括各自从表面延伸预定深度的p型和n型杂质区。 由于在杂质区域的底部发生pn结，所以在pn结中扩散耗尽层，从而降低位于较高位置处的交叉方向上的虚设区域和导电配线之间的寄生电容。 有源区中的p沟道晶体管和n沟道晶体管的杂质区和源/漏区同时由杂质注入形成。

公开(公告)号：US06267479B1

公开(公告)日：2001-07-31

申请号：US09241138

申请日：1999-02-02

申请人： Keiichi Yamada ,  Hiroshi Kawashima ,  Keiichi Higashitani

发明人： Keiichi Yamada ,  Hiroshi Kawashima ,  Keiichi Higashitani

IPC分类号： H01L31119

CPC分类号： H01L21/823807 ,  H01L21/823857 ,  H01L21/823892

摘要： There is described a semiconductor device which includes in a single chip a high withstanding voltage transistor and a low withstanding voltage transistor and which imparts each of the transistors with a relevant threshold voltage and a characteristic suitable for retarding hot carriers. Specifically, an impurity profile is imparted to a lightly-doped extension (LDDEX) region formed across a channel region of a low withstanding voltage NMOS transistor, and a different impurity profile is imparted to an LDDEX region formed across a channel region of a high withstanding voltage NMOS transistor. These impurity profiles bring the threshold voltages of the MOS transistors to individual relevant voltages and retard hot carriers in the individual MOS transistors.

摘要翻译： 描述了一种半导体器件，其在单个芯片中包括高耐压晶体管和低耐压晶体管，并且使每个晶体管具有适当的延迟热载流子的相关阈值电压和特性。 具体地说，杂质分布被赋予在低耐压NMOS晶体管的沟道区域上形成的轻掺杂延伸（LDDEX）区域，并且不同的杂质分布被赋予形成在高耐压的沟道区域上的LDDEX区域 电压NMOS晶体管。 这些杂质分布将MOS晶体管的阈值电压带到单独的相关电压并延迟各个MOS晶体管中的热载流子。

公开(公告)号：US06291870B1

公开(公告)日：2001-09-18

申请号：US09444557

申请日：1999-11-19

申请人： Hiroshi Kawashima ,  Keiichi Yamada ,  Keiichi Higashitani

发明人： Hiroshi Kawashima ,  Keiichi Yamada ,  Keiichi Higashitani

IPC分类号： H01L3300

CPC分类号： H01L21/76229 ,  H01L21/76819

摘要： A semiconductor device is implemented having dummy patterns arranged by designedly determining the ratio of area occupied by a protruded portion of an element formation region considering the deposited state of a buried insulating film which becomes an isolation insulating film. The ratio of area occupied by a protruded portion of a dummy pattern to a predetermined cell region is defined to be almost the same as the maximum or average value of ratios of areas occupied respectively by protruded element formation regions to a plurality of predetermined regions each including a plurality of predetermined cell regions.

摘要翻译： 考虑到成为隔离绝缘膜的埋入绝缘膜的沉积状态，半导体器件被实现为具有通过设计地确定元件形成区域的突出部分所占据的面积比而排列的虚拟图案。 将虚设图形的突出部分所占据的面积与预定单元区域的面积的比率定义为与突起元件形成区域分别占据的面积与多个预定区域的比率的最大值或平均值几乎相同， 多个预定单元区域。

公开(公告)号：US20050112832A1

公开(公告)日：2005-05-26

申请号：US10982903

申请日：2004-11-08

申请人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

发明人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/336 ,  H01L21/04 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L27/0629 ,  H01L28/20

摘要： A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

公开(公告)号：US06841459B2

公开(公告)日：2005-01-11

申请号：US10288458

申请日：2002-11-06

申请人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

发明人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/04 ,  H01L21/336

CPC分类号： H01L28/20 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/0629

摘要： A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

摘要翻译： 在将各种杂质植入到所述多晶硅膜中之后，在多晶硅膜中激活作为栅电极和电阻元件的各杂质的热处理被执行，所述多晶硅膜为栅电极，电阻元件涂覆有氧化物膜 多晶硅膜是栅电极和电阻元件。 这里，通过控制氧化膜的厚度来调节作为栅电极和电阻元件的多晶硅膜中各杂质的浓度。 从而调节杂质活化程度。

公开(公告)号：US06753246B2

公开(公告)日：2004-06-22

申请号：US10419770

申请日：2003-04-22

申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

IPC分类号： H01L214763

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

摘要翻译： 半导体器件包括半导体衬底，并且在半导体衬底中的元件隔离区域中具有间距小于第一A / A虚设图形的间距的第一有源区A / A虚拟图案和第二A / A虚拟图案 。 第一A / A虚拟图案的放置和第二A / A虚拟图案的放置在单独的步骤中进行。 半导体衬底可以被划分成多个网格区域，并且可以根据网格区域被位于其中的元素图案占据的区域而将虚设图案放置在每个网格区域中。

公开(公告)号：US06563148B2

公开(公告)日：2003-05-13

申请号：US09828981

申请日：2001-04-10

申请人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

发明人： Hiroshi Kawashima ,  Masakazu Okada ,  Takeshi Kitani ,  Motoshige Igarashi

IPC分类号： H01L2710

CPC分类号： H01L21/31053 ,  H01L21/76229

摘要： The semiconductor device includes a semiconductor substrate and, in an element isolating region in the semiconductor substrate, a first active area A/A dummy pattern and a second A/A dummy pattern having a pitch smaller than that of the first A/A dummy pattern. Placement of the first A/A dummy pattern and placement of the second A/A dummy pattern are carried out in separate steps. The semiconductor substrate may be divided into a plurality of mesh regions, and a dummy pattern may be placed in each mesh region according to an area of the mesh region being occupied by an element pattern located therein.

公开(公告)号：US09782377B2

公开(公告)日：2017-10-10

申请号：US10546158

申请日：2004-03-26

申请人： Kengo Akimoto ,  Yoshiko Ono ,  Hiroshi Kawashima ,  Katsuya Nagai

发明人： Kengo Akimoto ,  Yoshiko Ono ,  Hiroshi Kawashima ,  Katsuya Nagai

IPC分类号： A61K31/202 ,  A23L1/30 ,  A23L33/12

CPC分类号： A61K31/202 ,  A23L33/12

摘要： A composition having a normalizing action for infradian rhythm and/or a synchronization promoting action for circadian rhythm (biological clock) containing arachidonic acid and/or an arachidonic acid-containing compound.

公开(公告)号：US08923939B2

公开(公告)日：2014-12-30

申请号：US12622727

申请日：2009-11-20

申请人： Hiroshi Kawashima

发明人： Hiroshi Kawashima

IPC分类号： H01F6/06 ,  H01F6/04

CPC分类号： H01F6/04

摘要： A superconduction apparatus includes: a superconductor; a first vacuum vessel configured to accommodate said superconductor; a cooling unit which comprises a cold head configured to generate a temperature at which the superconductor is set to a superconduction state; and a second vacuum vessel configured to accommodate the cooling unit. The head and the superconductor are connected through a first connection hole which communicates the first vacuum vessel and the second vacuum vessel.

摘要翻译： 超导体装置包括：超导体; 构造成容纳所述超导体的第一真空容器; 冷却单元，其包括构造成产生将超导体设定为超导状态的温度的冷头; 以及构造成容纳冷却单元的第二真空容器。 头和超导体通过连接第一真空容器和第二真空容器的第一连接孔连接。