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    Computing network path delays so accurate absolute time can be forwarded from a server to a client
    1.
    发明授权
    Computing network path delays so accurate absolute time can be forwarded from a server to a client 有权
    计算网络路径延迟如此精确的绝对时间可以从服务器转发到客户端

    公开(公告)号：US06941109B2

    公开(公告)日：2005-09-06

    申请号：US10079251

    申请日：2002-02-19

    申请人： Hiroshi Matsushita ,  Paul W. McBurney

    发明人： Hiroshi Matsushita ,  Paul W. McBurney

    IPC分类号： G04G5/00 ,  G01S1/00 ,  G01S19/25 ,  G06F13/00 ,  H04J3/06 ,  H04B7/19

    CPC分类号： G01S19/256 ,  H04J3/0644 ,  H04J3/0667

    摘要： A navigation-satellite receiver support data network comprises a server connected to the Internet to provide initialization information to clients for faster cold starts. The server includes a GPS receiver that provides for tracking of a constellation of navigation satellites. When a client is started cold, time and frequency are initially unknown to it. Test messages are sent back and forth over the Internet and a path delay time is computed from the average of the quickest transit times. This yields the offset time between the server's time system and the client's time system. The server sends current time information to the client, and the computed path delay is added. The client can then compute correct time from the server and path delay information, and thereby select much sooner which satellites are correct to search.

    摘要翻译： 导航卫星接收机支持数据网络包括连接到因特网的服务器，以向客户端提供初始化信息以用于更快的冷启动。 服务器包括GPS接收器，用于跟踪导航卫星的星座。 当客户开始冷静时，时间和频率最初是未知的。 测试消息通过互联网来回发送，并且路径延迟时间是从最快的传输时间的平均值来计算的。 这产生了服务器的时间系统和客户端的时间系统之间的偏移时间。 服务器向客户端发送当前时间信息，并添加计算出的路径延迟。 然后，客户端可以从服务器和路径延迟信息计算正确的时间，从而选择更早的哪个卫星正确搜索。

    Software-compensated crystal oscillator
    2.
    发明授权
    Software-compensated crystal oscillator 有权
    软件补偿晶体振荡器

    公开(公告)号：US06509870B1

    公开(公告)日：2003-01-21

    申请号：US10079248

    申请日：2002-02-19

    申请人： Hiroshi Matsushita ,  Paul W. McBurney

    发明人： Hiroshi Matsushita ,  Paul W. McBurney

    IPC分类号： G01S502

    CPC分类号： G01S19/23 ,  H03J3/04 ,  H03L1/026 ,  H03L1/028

    摘要： A navigation-satellite receiver comprises a crystal oscillator that is affected by local ambient temperature in a repeatable way. After locking onto a GPS satellite, the receiver is used to calculate the true frequency bias of the local crystal oscillator. GPS-system lock provides an atomic-clock basis for such measurements of true frequency. The current temperature of the crystal is measured and recorded in association with the true frequency bias measurement. The data is then used to generate a ninth-order polynomial that describes the frequency drift of the crystal over temperature. Then during receiver initialization when the local reference oscillator is not in lock, the ambient temperature is measured and used to index the ninth-order polynomial to estimate the actual crystal frequency. Such frequency estimate is then used as a basis to find signal from visible SV's in an overhead constellation.

    摘要翻译： 导航卫星接收机包括以可重复的方式受局部环境温度影响的晶体振荡器。 锁定在GPS卫星上后，接收机用于计算局部晶体振荡器的真实频率偏置。 GPS系统锁为真实频率的这种测量提供了原子钟基础。 与真实的频率偏差测量相关联地测量和记录晶体的当前温度。 然后将数据用于生成描述晶体温度的频率漂移的九阶多项式。 然后在本地参考振荡器未锁定的接收机初始化期间，测量环境温度并用于对第九阶多项式进行索引以估计实际晶体频率。 然后，这种频率估计被用作在顶点星座中从可见的SV查找信号的基础。

    DEFECT ANALYSIS METHOD OF SEMICONDUCTOR DEVICE
    4.
    发明申请
    DEFECT ANALYSIS METHOD OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件缺陷分析方法

    公开(公告)号：US20120029679A1

    公开(公告)日：2012-02-02

    申请号：US13177127

    申请日：2011-07-06

    申请人： Hiroshi Matsushita

    发明人： Hiroshi Matsushita

    IPC分类号： G06F19/00

    CPC分类号： H01L22/20 ,  H01L22/12

    摘要： A defect analysis method of semiconductor device, wherein defect percentage data for each of inspection units within a wafer and information pieces regarding manufacturing conditions for the wafer are loaded into a computer; statistical testing of the defect percentage data with respect to the manufacturing conditions is performed using the computer; and results of the statistical testing are collected for each of the information pieces on the manufacturing conditions and outputted from the computer.

    摘要翻译： 半导体器件的缺陷分析方法，其中晶片内的每个检查单元的缺陷百分比数据和关于晶片的制造条件的信息片被加载到计算机中; 使用计算机进行关于制造条件的缺陷百分比数据的统计测试; 并且对于制造条件的每个信息收集统计测试的结果并从计算机输出。

    Method and system for managing semiconductor manufacturing device
    5.
    发明申请
    Method and system for managing semiconductor manufacturing device 审中-公开
    用于管理半导体制造装置的方法和系统

    公开(公告)号：US20110245956A1

    公开(公告)日：2011-10-06

    申请号：US13067542

    申请日：2011-06-08

    申请人： Hiroshi Matsushita ,  Junji Sugamoto ,  Masafumi Asano

    发明人： Hiroshi Matsushita ,  Junji Sugamoto ,  Masafumi Asano

    IPC分类号： G06F19/00

    CPC分类号： G05B19/41875 ,  G05B2219/32179 ,  G05B2219/32221 ,  G05B2219/45031 ,  Y02P90/22

    摘要： A management system includes a variable-period setting unit that sets a variable period in which quality-control values vary. Then, a retrieving unit retrieves events sandwiching the variable period. The events can be a maintenance of the semiconductor manufacturing device and/or a change of a correction value. An analysis-period setting unit sets an analysis period for analyzing a cause of variation of the quality-control values between the events retrieved by the retrieving unit.

    摘要翻译： 管理系统包括设定质量控制值变化的可变周期的可变周期设定部。 然后，检索单元检索夹着可变周期的事件。 这些事件可以是半导体制造装置的维护和/或校正值的改变。 分析周期设定单元设定用于分析由检索单元检索的事件之间的质量控制值的变化原因的分析期间。

    Management system of semiconductor fabrication apparatus, abnormality factor extraction method of semiconductor fabrication apparatus, and management method of the same
    6.
    发明授权
    Management system of semiconductor fabrication apparatus, abnormality factor extraction method of semiconductor fabrication apparatus, and management method of the same 失效
    半导体制造装置的管理系统，半导体制造装置的异常因子提取方法及其管理方法

    公开(公告)号：US07742834B2

    公开(公告)日：2010-06-22

    申请号：US11727824

    申请日：2007-03-28

    申请人： Hiroshi Matsushita ,  Junji Sugamoto ,  Masafumi Asano

    发明人： Hiroshi Matsushita ,  Junji Sugamoto ,  Masafumi Asano

    IPC分类号： G06F19/00 ,  G05B13/02 ,  H01L21/00 ,  G01N37/00

    CPC分类号： G05B19/41875 ,  G05B2219/32075 ,  G05B2219/32222 ,  G05B2219/45031 ,  Y02P90/22

    摘要： According to the present, there is proved a semiconductor fabrication apparatus management system having:a sensor which monitors and outputs a plurality of apparatus parameters of a semiconductor fabrication apparatus which fabricates a semiconductor device;a measurement unit which measures a dimensional value of the semiconductor device, and outputs the dimensional value as dimensional data;an apparatus parameter storage unit which stores the apparatus parameters;a dimensional data storage unit which stores the dimensional data;an apparatus parameter controller which calculates predicted dimensional data by extracting the dimensional data from the dimensional data storage unit, and controls at least one of the plurality of apparatus parameters on the basis of the predicted dimensional data; andan abnormality factor extraction unit which analyzes correlations between the controlled apparatus parameter and other apparatus parameters, and extracts an abnormal apparatus parameter on the basis of a calculated correlation coefficient.

    摘要翻译： 根据现在，已经证明了一种半导体制造装置管理系统，其具有：监视并输出制造半导体装置的半导体制造装置的多个装置参数的传感器; 测量单元，其测量半导体器件的尺寸值，并将该尺寸值作为尺寸数据输出; 装置参数存储单元，其存储所述装置参数; 存储尺寸数据的尺寸数据存储单元; 装置参数控制器，其通过从所述尺寸数据存储单元提取所述尺寸数据来计算预测尺寸数据，并且基于所述预测尺寸数据来控制所述多个装置参数中的至少一个; 以及异常因子提取单元，其分析受控设备参数和其他设备参数之间的相关性，并且基于计算的相关系数提取异常设备参数。

    Method for analyzing fail bit maps of wafers
    7.
    发明授权
    Method for analyzing fail bit maps of wafers 失效
    分析晶圆故障位图的方法

    公开(公告)号：US07138283B2

    公开(公告)日：2006-11-21

    申请号：US10865927

    申请日：2004-06-14

    申请人： Hiroshi Matsushita ,  Kenichi Kadota

    发明人： Hiroshi Matsushita ,  Kenichi Kadota

    IPC分类号： G01R31/26

    CPC分类号： G11C29/006 ,  G11C2029/0403 ,  G11C2029/4402 ,  G11C2029/5002

    摘要： A method of detecting a wafer failure includes extracting the wafer ID of a target wafer in the target lot from the lot ID, extracting the location information of a failure in the target wafer, calculating a to-be-quantified first wafer feature amount for unevenness of a wafer failure distribution, calculating a first lot feature amount for each target lot, extracting a fabrication process for the target lot and a fabrication apparatus, carrying out a significant test for the fabrication apparatus used in each fabrication process, and detecting the fabrication apparatus with a significant difference as a first abnormal apparatus.

    摘要翻译： 检测晶片故障的方法包括从批号ID提取目标批次中的目标晶片的晶片ID，提取目标晶片中的故障的位置信息，计算用于不均匀的待定量的第一晶片特征量 计算每个目标批次的第一批特征量，提取目标批次的制造过程和制造装置，对在每个制造过程中使用的制造装置进行显着测试，并检测制造装置 作为第一异常装置具有显着差异。

    System and method for identifying a manufacturing tool causing a fault
    8.
    发明申请
    System and method for identifying a manufacturing tool causing a fault 失效
    用于识别造成故障的制造工具的系统和方法

    公开(公告)号：US20050251365A1

    公开(公告)日：2005-11-10

    申请号：US11090217

    申请日：2005-03-28

    申请人： Hiroshi Matsushita ,  Kenichi Kadota

    发明人： Hiroshi Matsushita ,  Kenichi Kadota

    IPC分类号： G05B19/418 ,  G06F11/30 ,  G06Q50/00 ,  G06Q50/04 ,  H01L21/66

    CPC分类号： G05B19/4184 ,  G05B2219/31356 ,  G05B2219/32222 ,  Y02P90/10 ,  Y02P90/14 ,  Y02P90/22

    摘要： A system for identifying a manufacturing tool causing a failure, includes a data generating module generating factorial effect data, based on information on a failure lot group by using an orthogonal array, a chart generating module generating a factorial effect chart based on the factorial effect data, a selection module selecting failure lots caused by the same reason for a failure from among the failure lot group, based on the factorial effect chart, and an identification module identifying a manufacturing tool used as a common tool for the selected plurality of failure lots, based on history information of the manufacturing tool group.

    摘要翻译： 一种用于识别导致故障的制造工具的系统包括：数据生成模块，基于通过使用正交阵列的故障批次组的信息来生成因子效果数据;图表生成模块，基于所述因子效应数据生成阶乘效果图 选择模块，基于所述阶乘效应图，选择由所述失败批次群组中与故障相同原因造成的故障批次;以及识别模块，其识别用作所选择的多个故障批次的共同工具的制造工具， 根据制造工具组的历史信息。

    Method for analyzing fail bit maps of wafers
    9.
    发明申请
    Method for analyzing fail bit maps of wafers 失效
    分析晶圆故障位图的方法

    公开(公告)号：US20050021303A1

    公开(公告)日：2005-01-27

    申请号：US10865927

    申请日：2004-06-14

    申请人： Hiroshi Matsushita ,  Kenichi Kadota

    发明人： Hiroshi Matsushita ,  Kenichi Kadota

    IPC分类号： H01L21/66 ,  G06F11/30 ,  G11C29/00 ,  H01L21/02

    CPC分类号： G11C29/006 ,  G11C2029/0403 ,  G11C2029/4402 ,  G11C2029/5002

    摘要： A method of detecting a wafer failure includes extracting the wafer ID of a target wafer in the target lot from the lot ID, extracting the location information of a failure in the target wafer, calculating a to-be-quantified first wafer feature amount for unevenness of a wafer failure distribution, calculating a first lot feature amount for each target lot, extracting a fabrication process for the target lot and a fabrication apparatus, carrying out a significant test for the fabrication apparatus used in each fabrication process, and detecting the fabrication apparatus with a significant difference as a first abnormal apparatus.

    摘要翻译： 检测晶片故障的方法包括从批号ID提取目标批次中的目标晶片的晶片ID，提取目标晶片中的故障的位置信息，计算用于不均匀的待定量的第一晶片特征量 计算每个目标批次的第一批特征量，提取目标批次的制造过程和制造装置，对在每个制造过程中使用的制造装置进行显着测试，并检测制造装置 作为第一异常装置具有显着差异。