公开(公告)号：US5627987A

公开(公告)日：1997-05-06

申请号：US21098

申请日：1993-02-23

申请人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

发明人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F12/00

CPC分类号： G06F12/1458 ,  G06F12/109 ,  G06F12/1483 ,  G06F12/1491 ,  G06F2212/656

摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.

摘要翻译： 一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。 在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限 区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。 或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序， 将搜索与当前节目号匹配的那个。 此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

公开(公告)号：US5890189A

公开(公告)日：1999-03-30

申请号：US753944

申请日：1996-12-03

申请人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

发明人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F12/00

CPC分类号： G06F12/1458 ,  G06F12/109 ,  G06F12/1483 ,  G06F12/1491 ,  G06F2212/656

摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.

摘要翻译： 一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。 在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限 区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。 或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序， 将搜索与当前节目号匹配的那个。 此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

公开(公告)号：US20100064111A1

公开(公告)日：2010-03-11

申请号：US12555952

申请日：2009-09-09

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda ,  Masaki Miyagawa ,  Hiroshi Nozue ,  Kazuhiro Kawagome

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda ,  Masaki Miyagawa ,  Hiroshi Nozue ,  Kazuhiro Kawagome

IPC分类号： G06F12/00 ,  G06F12/16 ,  G06F12/02

CPC分类号： G06F12/0804 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/7201

摘要： A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

摘要翻译： 根据本发明的示例的设备包括接收来自处理器的写入目的地逻辑地址和写入目标数据的部分，写入目的地逻辑地址指示写入位置以将写入目标数据写入复合存储器，该复合存储器包括第一 存储器和非易失性第二存储器，确定与写入目的地逻辑地址相对应的写目的物理地址的部分，使得对第二存储器的访问次数小于对第一存储器的访问次数， 在存储部中存储将写入目的地逻辑地址与写入目的地物理地址相关联的地址转换数据以及将写入目标数据写入由写入目的地物理地址指示的复合存储器中的位置的部分。

公开(公告)号：US09280466B2

公开(公告)日：2016-03-08

申请号：US12555952

申请日：2009-09-09

申请人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda ,  Masaki Miyagawa ,  Hiroshi Nozue ,  Kazuhiro Kawagome

发明人： Atsushi Kunimatsu ,  Hiroto Nakai ,  Hiroyuki Sakamoto ,  Kenichi Maeda ,  Masaki Miyagawa ,  Hiroshi Nozue ,  Kazuhiro Kawagome

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0804 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/0888 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/7201

摘要： A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address.

摘要翻译： 根据本发明的示例的设备包括接收来自处理器的写入目的地逻辑地址和写入目标数据的部分，写入目的地逻辑地址指示写入位置以将写入目标数据写入复合存储器，该复合存储器包括第一 存储器和非易失性第二存储器，确定与写入目的地逻辑地址相对应的写目的物理地址的部分，使得对第二存储器的访问次数小于对第一存储器的访问次数， 在存储部中存储将写入目的地逻辑地址与写入目的地物理地址相关联的地址转换数据以及将写入目标数据写入由写入目的地物理地址指示的复合存储器中的位置的部分。

公开(公告)号：US6034375A

公开(公告)日：2000-03-07

申请号：US46037

申请日：1998-03-23

申请人： Hiroshi Nozue

发明人： Hiroshi Nozue

IPC分类号： H01L21/027 ,  G03F7/20 ,  H01J37/304

CPC分类号： H01J37/3045 ,  H01J2237/31735

摘要： There is provided a method of aligning a semiconductor substrate with a base stage on which the semiconductor substrate is placed, in the process of forming a circuit pattern directly onto the semiconductor substrate with electron beams, the method including the steps of (a) scanning across an alignment mark formed on a surface of the semiconductor substrate with electron beams with a scanning angle, defined as an angle between a direction of the electron beams and a reference direction, being varied, (b) calculating a width of the alignment mark along a scanning direction for each of scanning angles, and (c) determining a minimum width among widths calculated in the step (b), and defining a scanning angle associated with the minimum width as an angular gap between the semiconductor substrate and the base stage. In accordance with the above-mentioned method, it is possible to align a semiconductor substrate with an X-Y stage with the less number of movements of the X-Y stage, which ensures a higher efficiency in exposing a semiconductor substrate to electron beams.

摘要翻译： 提供了一种使用电子束将电路图案直接形成在半导体衬底上的过程中半导体衬底与其上放置有半导体衬底的基底台对准的方法，该方法包括以下步骤：（a）扫描 在半导体衬底的表面上形成有以电子束的方向和基准方向之间的角度定义为扫描角的电子束的对准标记变化，（b）计算对准标记沿着 扫描方向，以及（c）确定在步骤（b）中计算出的宽度中的最小宽度，并将与最小宽度相关联的扫描角度定义为半导体衬底和基底台之间的角度间隙。 根据上述方法，可以使半导体衬底与X-Y平台的移动次数较少的X-Y平台对齐，这确保了将半导体衬底暴露于电子束的更高的效率。

公开(公告)号：US5968686A

公开(公告)日：1999-10-19

申请号：US910424

申请日：1997-08-13

申请人： Yasuhisa Yamada ,  Hiroshi Nozue

发明人： Yasuhisa Yamada ,  Hiroshi Nozue

IPC分类号： H01L21/027 ,  G03F7/20 ,  H01J37/317 ,  G03F9/00

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F1/20 ,  G03F7/2047 ,  H01J37/3174 ,  H01J2237/31788 ,  H01J2237/31794

摘要： An electron-beam exposure mask that is able to realize the required pattern transfer accuracy independent of the deflection distortion and aberration of an electron beam. This mask includes a substrate with a first area and a second area, a first plurality of cell apertures formed in the first area of the substrate, and a second plurality of cell apertures formed in the second area of the substrate. The first area of the substrate is designed so that a charged-beam irradiated to the first area has a deflection angle less than a reference angle. The second area of the substrate is designed so that a charged-beam irradiated to the second area has a deflection angle equal to or greater than the reference angle. Each of the first plurality of cell apertures corresponds to fine patterns necessitating high pattern transfer accuracy. Each of the second plurality of cell apertures corresponds to rough patterns unnecessitating the high pattern transfer accuracy.

摘要翻译： 能够实现与电子束的偏转失真和像差无关的所需图案转印精度的电子束曝光掩模。 该掩模包括具有第一区域和第二区域的基板，形成在基板的第一区域中的第一多个单元孔，以及形成在基板的第二区域中的第二多个单元孔。 衬底的第一区域被设计成使得照射到第一区域的带电束具有小于参考角的偏转角。 衬底的第二区域被设计成使得照射到第二区域的带电束具有等于或大于参考角的偏转角。 第一多个单元孔径中的每一个对应于需要高图案转印精度的精细图案。 第二多个单元孔径中的每一个对应于不需要高图案转印精度的粗糙图案。

公开(公告)号：US20060068298A1

公开(公告)日：2006-03-30

申请号：US10535165

申请日：2003-12-01

申请人： Hisatake Sano ,  Morihisa Hoga ,  Yukio Iimura ,  Yuki Aritsuka ,  Masaaki Kurihara ,  Hiroshi Nozue ,  Akira Yoshida

发明人： Hisatake Sano ,  Morihisa Hoga ,  Yukio Iimura ,  Yuki Aritsuka ,  Masaaki Kurihara ,  Hiroshi Nozue ,  Akira Yoshida

IPC分类号： G03F1/00

CPC分类号： G03F1/78 ,  G03F1/20 ,  G03F1/22 ,  G03F1/24

摘要： It is an object of the present invention to effectively manufacture a charged-particle beam lithography mask, an X-ray lithography mask, or an extreme ultraviolet beam lithography mask by using, for example, an existing writer such as an electron beam writer for photomasks, while achieving improvement in processing accuracy of a mask pattern. A lithography mask (1) comprises a substrate (2) which has a lower surface provided substantially at the center thereof with an opening (3) and a self-supporting membrane (m) having a pattern region (4) substantially at the center of an upper surface of the substrate (2) corresponding to the opening (3). The self-supporting membrane (m) is provided with through-holes (h) of a mask pattern in it or an absorber or scatterer of a mask pattern on it, and the pattern region (4) and a peripheral region around the pattern region (5) are in one plane.

摘要翻译： 本发明的目的是通过使用例如诸如用于光掩模的电子束写入器的现有写入器来有效地制造带电粒子束光刻掩模，X射线光刻掩模或极紫外光束光刻掩模 同时实现掩模图案的处理精度的提高。 光刻掩模（1）包括基底（2），基底（2）具有基本上在其中心处设置有开口（3）的下表面和具有基本上位于中心的图案区域（4）的自支撑膜（m） 所述基板（2）的与所述开口（3）对应的上表面。 自支撑膜（m）在其上设置有掩模图案的通孔（h）或其上的掩模图案的吸收体或散射体，图案区域（4）和图案区域周围的周边区域 （5）在一个平面上。

公开(公告)号：US6042971A

公开(公告)日：2000-03-28

申请号：US006503

申请日：1998-01-14

申请人： Takao Tamura ,  Hiroshi Yamashita ,  Ken Nakajima ,  Hiroshi Nozue

发明人： Takao Tamura ,  Hiroshi Yamashita ,  Ken Nakajima ,  Hiroshi Nozue

IPC分类号： G03F1/20 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F1/20

摘要： The present invention consists in a method of creating an EB mask for electron beam image drawing, comprising: a step of extracting patterns for forming on an EB mask from design data stored in means for storage; a step of calculating an aperture area of an aperture section requested in an EB mask, using the design data contained in the extracted cell; a step of generating cell data for aperture creation using the value of this aperture area; and a step of forming a basic aperture pattern in an EB mask using this cell data for aperture creation.

摘要翻译： 本发明在于一种创建用于电子束图像绘制的EB掩模的方法，包括：从存储在存储器中的设计数据中提取用于在EB掩模上形成的图案的步骤; 使用包含在所提取的单元中的设计数据来计算EB掩模中请求的孔径区域的孔径面积的步骤; 使用该开口区域的值生成用于孔径创建的单元数据的步骤; 以及使用这种用于孔径创建的单元数据在EB掩模中形成基本孔径图案的步骤。

公开(公告)号：US5759722A

公开(公告)日：1998-06-02

申请号：US585718

申请日：1996-01-16

申请人： Hiroshi Nozue

发明人： Hiroshi Nozue

IPC分类号： H01L21/306 ,  G03F1/20 ,  G03F1/68 ,  G03F7/20 ,  H01J37/09 ,  H01L21/027 ,  G03F9/00

CPC分类号： G03F7/2047 ,  H01J37/09 ,  H01J2237/0453 ,  H01J2237/3175

摘要： The aperture structure is for cell projection writing of patterns on a semiconductor substrate by an electron beam. The aperture structure includes a wafer, and a plurality of aperture patterns formed in the wafer. The aperture patterns are positioned and structured such that a thermal coefficient of a front side of the wafer and that of a back side of the wafer are the same as each other. The aperture patterns are positioned in a central portion and are symmetrically shaped in the depth direction of the base. For fabricating the aperture structure, the front side of the wafer is etched, or the front side and the back side of the wafer are etched, and the aperture patterns are formed in the etched portion or portions. The back side of the wafer is etched to the same depth as the front side. The aperture structure does not become warped, and the accuracy of generating patterns on a wafer with electron beams is greatly enhanced.

摘要翻译： 孔结构用于通过电子束在半导体衬底上的图案的单元投影写入。 孔结构包括晶片和形成在晶片中的多个孔径图案。 孔径图案被定位和构造使得晶片的前侧的热系数和晶片的背面的热系数彼此相同。 孔径图案位于中心部分并且在基部的深度方向上对称成形。 为了制造孔结构，蚀刻晶片的前侧，或蚀刻晶片的前侧和后侧，并且在蚀刻部分中形成孔径图案。 将晶片的背面蚀刻到与前侧相同的深度。 孔结构不会翘曲，并且大大提高了用电子束在晶片上产生图案的精度。

公开(公告)号：US5452053A

公开(公告)日：1995-09-19

申请号：US307155

申请日：1994-09-16

申请人： Hiroshi Nozue

发明人： Hiroshi Nozue

IPC分类号： G03F7/20 ,  H01L21/027 ,  G03B27/72

CPC分类号： G03F7/701 ,  G03F7/70283

摘要： In a wafer stepper for fabricating semiconductor ICs (Integrated Circuits), a glass substrate carries thereon a plurality of octagonal patterns formed of a transmissive material. With such a glass substrate, the stepper diffracts light not only in X and Y directions but also in 45.degree. directions and 135.degree. directions. A mask pattern is transferred to a wafer with enhanced resolution and depth of focus.

摘要翻译： 在用于制造半导体IC（集成电路）的晶片步进器中，玻璃基板上承载由透射材料形成的多个八边形图案。 对于这种玻璃基板，步进器不仅在X方向和Y方向上衍射光，而且在45度方向和135度方向上衍射光。 掩模图案被转移到具有增强的分辨率和聚焦深度的晶片。