公开(公告)号：US5890189A

公开(公告)日：1999-03-30

申请号：US753944

申请日：1996-12-03

申请人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

发明人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F12/00

CPC分类号： G06F12/1458 ,  G06F12/109 ,  G06F12/1483 ,  G06F12/1491 ,  G06F2212/656

摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.

摘要翻译： 一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。 在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限 区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。 或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序， 将搜索与当前节目号匹配的那个。 此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

公开(公告)号：US5627987A

公开(公告)日：1997-05-06

申请号：US21098

申请日：1993-02-23

申请人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

发明人： Hiroshi Nozue ,  Mitsuo Saito ,  Kenichi Maeda ,  Shigehiro Asano ,  Toshio Okamoto ,  Shin Sungho ,  Hideo Segawa

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F12/00

CPC分类号： G06F12/1458 ,  G06F12/109 ,  G06F12/1483 ,  G06F12/1491 ,  G06F2212/656

摘要： A memory management and protection system for realizing a high speed execution and a proper and flexible memory access control for multiple programs sharing an identical logical address space. In the system, the memory access is permitted according to a segment identifier identifying a segment in the logical address space, and a memory protection information for a region in each segment including a target right permission to indicate assigned rights to make a memory access from the region to each of the segments, and an execution permission to indicate a type of the memory access permitted by the right permission. Alternatively, a memory access can be permitted by using an access control list to be attached to each address table entry, which stores a plurality of program numbers identifying programs which are permitted to make accesses to the logical address stored in each address table entry, among which one that matches with the current program number is to be searched. Also, it is preferable to allocate a plurality of programs within a limit of available memory protection capacity to an identical logical address space, without any overlap between adjacently allocated address regions.

摘要翻译： 一种用于实现高速执行的存储器管理和保护系统，以及用于共享相同逻辑地址空间的多个程序的适当且灵活的存储器访问控制。 在系统中，根据标识逻辑地址空间中的段的段标识符，允许存储器访问，以及每个区段中的区域的存储器保护信息，包括目标权限，以指示从存储器访问的指定的权限 区域，以及用于指示由权限许可允许的存储器访问的类型的执行许可。 或者，可以通过使用附加到每个地址表条目的访问控制列表来允许存储器访问，每个地址表条目存储多个程序号，标识被允许访问存储在每个地址表条目中的逻辑地址的程序， 将搜索与当前节目号匹配的那个。 此外，优选地，在可用存储器保护容量的限制内将多个程序分配给相同的逻辑地址空间，而不会在相邻分配的地址区域之间发生任何重叠。

公开(公告)号：US06820187B2

公开(公告)日：2004-11-16

申请号：US09989028

申请日：2001-11-21

申请人： Shigehiro Asano ,  Mitsuo Saito

发明人： Shigehiro Asano ,  Mitsuo Saito

IPC分类号： G06F15163

CPC分类号： G06F13/28

摘要： A multiprocessor system including a master processor, a plurality of processor elements, each of which is provided with a local memory, the processor elements being controlled in accordance with commands from the foregoing master processor, and a global memory shared by the plurality of processor elements is disclosed. The processor elements are provided with a command pooling buffer capable of accumulating a plurality of commands, respectively. DMA controllers are also provided with a command pooling buffer capable of accumulating a plurality of commands, respectively. The master processor persistently issues a plurality of commands to the DMA controller and each processor element. A counter array manages the number of the issued commands which have received no response. When the responses are returned with respect to all issued commands, the counter array notifies the master processor of this.

摘要翻译： 一种多处理器系统，包括主处理器，多个处理器元件，每个处理器元件具有本地存储器，处理器元件根据来自前述主处理器的命令进行控制，以及由多个处理器元件共享的全局存储器 被披露。 处理器元件设置有分别能够累积多个命令的命令池缓冲器。 DMA控制器还具有能分别累积多个命令的命令池缓冲器。 主处理器持续向DMA控制器和每个处理器元件发出多个命令。 计数器阵列管理没有响应的已发出命令的数量。 当相对于所有发出的命令返回响应时，计数器阵列通知主处理器。

公开(公告)号：US08812774B2

公开(公告)日：2014-08-19

申请号：US13217461

申请日：2011-08-25

申请人： Shigehiro Asano ,  Shinichi Kanno ,  Kazuhiro Fukutomi ,  Akira Yamaga

发明人： Shigehiro Asano ,  Shinichi Kanno ,  Kazuhiro Fukutomi ,  Akira Yamaga

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F11/1068

摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.

摘要翻译： 根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子 接收单元; 发电机组; 第二个表 和书写单位。 第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。 生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。 在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。 当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。

公开(公告)号：US08612824B2

公开(公告)日：2013-12-17

申请号：US13038804

申请日：2011-03-02

申请人： Kazumasa Yamamoto ,  Shinichi Kanno ,  Shigehiro Asano ,  Hiroyuki Nagashima

发明人： Kazumasa Yamamoto ,  Shinichi Kanno ,  Shigehiro Asano ,  Hiroyuki Nagashima

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G11C16/3418 ,  G11C16/00 ,  G11C29/028

摘要： A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, respectively.

摘要翻译： 半导体存储器件包括：多个半导体存储器芯片，用于根据累积电荷的量存储信息; 多个参数存储单元，与半导体存储器芯片对应地设置，每个参数用于存储定义用于将信息写入或从相应的一个半导体存储器芯片读取信息的信号的电特性的参数; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量来分别改变参数，并将分别写入参数存储单元的参数进行写入。

公开(公告)号：US08397017B2

公开(公告)日：2013-03-12

申请号：US12723846

申请日：2010-03-15

申请人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kenichiro Yoshii ,  Kazuhiro Fukutomi ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G06F13/00

CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/7207

摘要： A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information.

摘要翻译： 易失性管理存储器存储用于管理存储介质的使用状态的管理信息。 管理信息存储单元将管理信息分成多个分割片，并将它们分别存储在存储介质中。 主控制器在存储分割片的同时从主机装置接收命令，根据存储各分割片之间的命令对存储介质执行数据处理，根据数据更新分割成分割片的管理信息 处理内容，并创建表示管理信息的更新内容的日志。 日志存储单元将日志存储在存储介质中。 恢复单元将存储在存储介质中的分割信息作为管理信息读取到管理存储器，根据存储在存储介质中的日志更新管理信息，并恢复更新的管理信息。

公开(公告)号：US08359457B2

公开(公告)日：2013-01-22

申请号：US12372011

申请日：2009-02-17

申请人： Takashi Yoshikawa ,  Shigehiro Asano

发明人： Takashi Yoshikawa ,  Shigehiro Asano

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F9/3879 ,  G06F9/3897 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the dynamically reconfigurable circuits includes a processing unit that performs a data computation, an updating unit that updates the reconfiguration information, and a repetition controlling unit that determines whether to repeat the computation and controls the data and the reconfiguration information.

摘要翻译： 半导体器件包括控制器和多个在控制器下串联连接的可动态可重构电路，以以管道的方式执行操作。 控制器将数据和重配置信息输入到动态可重配置电路中的第一个。 每个动态可重配置电路包括执行数据计算的处理单元，更新重新配置信息的更新单元以及确定是否重复计算并控制数据和重新配置信息的重复控制单元。

公开(公告)号：US20120072811A1

公开(公告)日：2012-03-22

申请号：US13035194

申请日：2011-02-25

申请人： Kazuhiro FUKUTOMI ,  Hiroshi Yao ,  Shinichi Kanno ,  Shigehiro Asano ,  Toshikatsu Hida ,  Yasuhiro Kimura

发明人： Kazuhiro FUKUTOMI ,  Hiroshi Yao ,  Shinichi Kanno ,  Shigehiro Asano ,  Toshikatsu Hida ,  Yasuhiro Kimura

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： G06F11/108 ,  G06F2211/1059 ,  G06F2211/1073 ,  G06F2211/1092

摘要： According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.

摘要翻译： 根据一个实施例，控制器控制对包括第一数据存储单元和第二数据存储单元的存储装置的写入和读取。 第二数据存储单元存储用户数据和用户数据的奇偶校验数据。 第一数据存储单元存储奇偶校验数据。 控制器包括奇偶校验更新单元和奇偶校验写入单元。 当更新奇偶校验数据时，奇偶校验更新单元将更新的奇偶校验数据写入第一数据存储单元。 当满足特定要求时，奇偶写入单元读取写入第一数据存储单元中的奇偶校验数据，并将读出的奇偶校验数据写入第二数据存储单元。

公开(公告)号：US20120030528A1

公开(公告)日：2012-02-02

申请号：US13270788

申请日：2011-10-11

申请人： Toshikatsu HIDA ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

发明人： Toshikatsu HIDA ,  Shinichi Kanno ,  Hirokuni Yano ,  Kazuya Kitsunai ,  Shigehiro Asano ,  Junji Yano

IPC分类号： G06F12/16 ,  G06F11/36

CPC分类号： G06F11/1412 ,  G06F11/1068 ,  G06F11/1402 ,  G06F12/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431

摘要： As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

摘要翻译： 作为可以有效地执行刷新操作的半导体存储装置，提供了一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除单元，以及监视数据的错误计数的控制单元 存储在从所述块中选择的监视块和所述监视块中的刷新数据中，其中所述错误计数等于或大于阈值。

公开(公告)号：US07984325B2

公开(公告)日：2011-07-19

申请号：US12398608

申请日：2009-03-05

申请人： Kazuhiro Fukutomi ,  Hideaki Sato ,  Shinichi Kanno ,  Shigehiro Asano

发明人： Kazuhiro Fukutomi ,  Hideaki Sato ,  Shinichi Kanno ,  Shigehiro Asano

IPC分类号： G06F11/00

CPC分类号： G06F11/108 ,  G06F11/1068

摘要： When data in one semiconductor memory device is corrupted during a padding process by a padding unit and the data cannot be recovered even by using an error correcting code for correcting a data error, a storage control device issues a data recovery request to a data recovery device. The data recovery device reads the data from other semiconductor memory device in response to the data recovery request to recover the data, and returns a recovery result to the padding unit in the storage control device to perform the padding process.

摘要翻译： 当一个半导体存储器件中的数据在填补单元的填充处理期间被破坏时，即使通过使用用于校正数据错误的纠错码也不能恢复数据，存储控制装置向数据恢复装置发出数据恢复请求 。 数据恢复装置响应于数据恢复请求从其他半导体存储装置读取数据以恢复数据，并将恢复结果返回到存储控制装置中的填充单元以执行填充处理。