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公开(公告)号：US20050068059A1
公开(公告)日：2005-03-31
申请号：US10962893
申请日：2004-10-12
申请人： Hiroshi Takahashi , Akihiro Takegama , Yutaka Toyonoh , Kaoru Awaka , Tsuyoshi Tanaka , Rimon Ikeno
发明人： Hiroshi Takahashi , Akihiro Takegama , Yutaka Toyonoh , Kaoru Awaka , Tsuyoshi Tanaka , Rimon Ikeno
IPC分类号： H01L21/822 , G11C5/14 , H01L27/04 , H01L31/0336 , H03K17/687 , H03K19/00 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00315 , G11C5/14 , H03K19/0016
摘要： A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage Vdd is applied to the gate of transistor MP0, a voltage lower than the source voltage is applied to the source, and bulk bias voltage VB equal to or higher than source voltage Vdd is applied to the channel region in order to minimize the drain current of transistor MP0, so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.
摘要翻译： 一种半导体集成电路，其中电路面积可以最小化，并且在待机状态期间可以可靠地检测缺陷，同时保持栅氧化膜的可靠性。 开关电路20设置在逻辑电路10和源电压Vdd供电端子之间。 在工作状态下，将0V电压施加到开关电路20的晶体管MP0的栅极，并将等于或略低于源极电压Vdd的偏置电压VB施加到其沟道区，以便降低晶体管的阈值电压 MP0并提高其目前的驾驶能力。 在待机状态下，将等于源极电压Vdd的电压施加到晶体管MP0的栅极，将低于源极电压的电压施加到源极，施加等于或高于源极电压Vdd的体偏置电压Vdd 到沟道区域，以使晶体管MP0的漏极电流最小化，使得逻辑电路10的电流路径被切断，并且抑制了泄漏电流的发生。
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公开(公告)号：US06850103B2
公开(公告)日：2005-02-01
申请号：US10259128
申请日：2002-09-27
申请人： Rimon Ikeno , Kaoru Awaka , Tsuyoshi Tanaka , Hiroshi Takahashi , Yutaka Toyonoh , Akihiro Takegama
发明人： Rimon Ikeno , Kaoru Awaka , Tsuyoshi Tanaka , Hiroshi Takahashi , Yutaka Toyonoh , Akihiro Takegama
CPC分类号： H03K3/0375 , H03K3/012
摘要： This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch transistors. The techniques require changes only in the circuit configuration. Neither higher cost technology such as multiple-threshold LVT/HVT transistors nor special control circuits are needed.
摘要翻译： 本发明描述了提供用于在具有开关晶体管的单步锁存器中实现可靠数据保持和低泄漏电流的装置的电路技术。 这些技术只需要在电路配置中进行更改。 既不需要诸如多阈值LVT / HVT晶体管的高成本技术，也不需要特殊的控制电路。
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公开(公告)号：US06864708B2
公开(公告)日：2005-03-08
申请号：US10200719
申请日：2002-07-22
申请人： Hiroshi Takahashi , Akihiro Takegama , Yutaka Toyonoh , Kaoru Awaka , Tsuyoshi Tanaka , Rimon Ikeno
发明人： Hiroshi Takahashi , Akihiro Takegama , Yutaka Toyonoh , Kaoru Awaka , Tsuyoshi Tanaka , Rimon Ikeno
IPC分类号： H01L21/822 , G11C5/14 , H01L27/04 , H01L31/0336 , H03K17/687 , H03K19/00 , H03K19/003 , H03K19/0948
CPC分类号： H03K19/00315 , G11C5/14 , H03K19/0016
摘要： A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability. While in a standby status, a voltage equal to source voltage Vdd is applied to the gate of transistor MP0, a voltage lower than the source voltage is applied to the source, and bulk bias voltage VB equal to or higher than source voltage Vdd is applied to the channel region in order to minimize the drain current of transistor MP0, so that current path of logic circuit 10 is cut off, and the occurrence of leakage current is suppressed.
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公开(公告)号：US06741098B2
公开(公告)日：2004-05-25
申请号：US09884662
申请日：2001-06-19
申请人： Hiroshi Takahashi , Yutaka Toyonoh , Akihiro Takegama , Osamu Handa , Rimon Ikeno , Kaoru Awaka , Tsuyoshi Tanaka
发明人： Hiroshi Takahashi , Yutaka Toyonoh , Akihiro Takegama , Osamu Handa , Rimon Ikeno , Kaoru Awaka , Tsuyoshi Tanaka
IPC分类号： H03K301
CPC分类号： H01L27/0928 , H03K19/0016
摘要： A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P2 and P3 which have different voltages applied to the respective sources and the mode control signal input to the gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby. Consequently, high speed and low power consumption can be realized.
摘要翻译： 一种可以将制造成本和布局面积增加到最低限度的半导体电路，并且可以实现高速度和低功耗。 通过包括施加到各个源的不同电压的PMOS晶体管P2和P3的偏置电压供给电路和输入到门的模式控制信号，对应于模式控制信号产生具有不同电平的偏置电压。 产生的偏置电压被提供给PMOS晶体管的n阱。 在操作期间，将与工作电压几乎相同的偏置电压施加到PMOS晶体管的n阱。 在待机期间，将高于工作电压的偏置电压提供给PMOS晶体管的上述n阱。 以这种方式，晶体管的驱动电流可以在工作期间保持在高电平，同时可以在待机期间抑制晶体管的漏电流。 因此，可以实现高速度和低功耗。
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公开(公告)号：US06603328B2
公开(公告)日：2003-08-05
申请号：US09974696
申请日：2001-10-10
申请人： Hiroshi Takahashi , Osamu Handa , Akihiro Takegama , Yutaka Toyonoh , Kaoru Awaka , Rimon Ikeno , Tsuyoshi Tanaka
发明人： Hiroshi Takahashi , Osamu Handa , Akihiro Takegama , Yutaka Toyonoh , Kaoru Awaka , Rimon Ikeno , Tsuyoshi Tanaka
IPC分类号： G01R3126
CPC分类号： G01R31/31721 , G01R31/3008 , H03K19/00361
摘要： The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2. In this way, the leakage current can be lessened on a low level, and whether the semiconductor integrated circuit is passed or defective can be judged from the results of the current measurement.
摘要翻译： 本发明的目的是提供一种半导体集成电路，其可以将电路区域中的解决方案减少到最小必要水平，并且可以减少待机状态下的泄漏电流，从而降低功耗，并且允许Iddq 测试以确定是否通过或有缺陷。 设置由低阈值电压晶体管构成的逻辑电路10和由具有标准阈值电压的晶体管构成的开关电路20。 在操作中，开关电路导通，驱动电流被馈送到逻辑电路10.另一方面，在待机模式下，开关电路断开，漏电流的路径被切断为 减少漏电流的产生。 在Iddq测试的情况下，不同的体偏置电压通过焊盘P1和P2从IC测试器施加到PMOS晶体管和NMOS晶体管的沟道区。 以这种方式，可以根据电流测量的结果来判断漏电流是否在低电平，并且半导体集成电路是否通过还是有缺陷。
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公开(公告)号：US20050177611A1
公开(公告)日：2005-08-11
申请号：US11013118
申请日：2004-12-14
摘要： The objective of this invention is to provide a type of addition circuit that can perform addition at a high speed without increasing power consumption, as well as a type of multiplication circuit and a type of multiplication/addition circuit having said addition circuit as the last step. It has a characteristic feature that the delay in a signal input from a Wallace tree to the addition circuit in the last step is maximum in the intermediate bit range, and it is smaller in the lower and upper bit ranges. In the lower bit range, addition is performed by means of 1-level carry increment adder 1 with a larger delay in carry propagation to the upper place. In the intermediate bit range, addition is performed by means of 2-level carry increment adder 1 having a carry propagation speed higher than that in said lower bit range. In the upper bit range, addition is performed by means of high-speed carry select adder 3. In this way, because addition is performed using addition schemes matched to the trend of delay in the signal input timing in the various bit ranges, it is possible to perform computing at high speed while the circuit scale and power consumption are reduced.
摘要翻译： 本发明的目的是提供一种可以在不增加功耗的情况下高速执行相加的加法电路，以及具有所述加法电路作为最后步骤的乘法电路和乘法/加法电路的一种类型 。 它具有以下特征：在最后一步中从华莱士树到加法电路输入的信号的延迟在中间位范围内是最大的，并且在较低和较高位范围内较小。 在较低位范围内，通过1电平进位增量加法器1执行加法，在进位传播到较高位置时延迟较大。 在中间位范围内，通过具有高于所述较低位范围内的进位传播速度的进位传播速度的2电平进位增量加法器1执行相加。 在高比特范围内，通过高速进位选择加法器3进行相加。这样，由于使用与各种比特范围内的信号输入定时的延迟趋势相匹配的相加方案进行加法，所以是 可以在电路规模和功耗降低的同时高速执行计算。
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公开(公告)号：US07035893B2
公开(公告)日：2006-04-25
申请号：US10954554
申请日：2004-09-30
申请人： Kaoru Awaka , Yutaka Toyonoh , Hiroshi Takahashi
发明人： Kaoru Awaka , Yutaka Toyonoh , Hiroshi Takahashi
IPC分类号： G06F7/50
CPC分类号： G06F7/607 , H03K19/215
摘要： A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight. In another embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than eight and a successive compressor critical transistor stage path level within the successive compressor is less than seven.
摘要翻译： 根据本发明实施例的乘法器的压缩机包括第一压缩机，其中第一压缩机包括第一多个输入。 第一压缩机还包括求和输出，第一进位位输出; 以及将所述第一多个输入中的每一个连接到所述求和输出的第一多个晶体管路径。 压缩机还包括连续的压缩机，其中连续的压缩机包括第二多个输入和多个连续的晶体管路径，将第一多个输入中的至少一个连接到第一进位位输出，并将第一进位位输出连接到 第二多个输入中的至少一个。 在本发明的一个实施例中，第一压缩机内的第一压缩机关键晶体管级路径电平小于七，并且连续压缩机内连续的压缩机关键晶体管级通路电平小于八。 在本发明的另一个实施例中，第一压缩机内的第一压缩机关键晶体管级路径电平小于八，并且连续压缩机内连续的压缩机关键晶体管级通路电平小于七。
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公开(公告)号：US07039667B1
公开(公告)日：2006-05-02
申请号：US09960348
申请日：2001-09-24
申请人： Kaoru Awaka , Yutaka Toyonoh , Hiroshi Takahashi
发明人： Kaoru Awaka , Yutaka Toyonoh , Hiroshi Takahashi
IPC分类号： G06F7/50
CPC分类号： G06F7/607 , H03K19/215
摘要： A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight. In another embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than eight and a successive compressor critical transistor stage path level within the successive compressor is less than seven.
摘要翻译： 根据本发明实施例的乘法器的压缩机包括第一压缩机，其中第一压缩机包括第一多个输入。 第一压缩机还包括求和输出，第一进位位输出; 以及将所述第一多个输入中的每一个连接到所述求和输出的第一多个晶体管路径。 压缩机还包括连续的压缩机，其中连续的压缩机包括第二多个输入和多个连续的晶体管路径，将第一多个输入中的至少一个连接到第一进位位输出，并将第一进位位输出连接到 第二多个输入中的至少一个。 在本发明的一个实施例中，第一压缩机内的第一压缩机关键晶体管级路径电平小于七，并且连续压缩机内连续的压缩机关键晶体管级通路电平小于八。 在本发明的另一个实施例中，第一压缩机内的第一压缩机关键晶体管级路径电平小于八，并且连续压缩机内连续的压缩机关键晶体管级通路电平小于七。
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公开(公告)号：US20050044125A1
公开(公告)日：2005-02-24
申请号：US10954554
申请日：2004-09-30
申请人： Kaoru Awaka , Yutaka Toyonoh , Hiroshi Takahashi
发明人： Kaoru Awaka , Yutaka Toyonoh , Hiroshi Takahashi
CPC分类号： G06F7/607 , H03K19/215
摘要： A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight. In another embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than eight and a successive compressor critical transistor stage path level within the successive compressor is less than seven.
摘要翻译： 根据本发明实施例的乘法器的压缩机包括第一压缩机，其中第一压缩机包括第一多个输入。 第一压缩机还包括求和输出，第一进位位输出; 以及将所述第一多个输入中的每一个连接到所述求和输出的第一多个晶体管路径。 压缩机还包括连续的压缩机，其中连续的压缩机包括第二多个输入和多个连续的晶体管路径，将第一多个输入中的至少一个连接到第一进位位输出，并将第一进位位输出连接到 第二多个输入中的至少一个。 在本发明的一个实施例中，第一压缩机内的第一压缩机关键晶体管级路径电平小于七，并且连续压缩机内连续的压缩机关键晶体管级通路电平小于八。 在本发明的另一个实施例中，第一压缩机内的第一压缩机关键晶体管级路径电平小于八，并且连续压缩机内连续的压缩机关键晶体管级通路电平小于七。
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公开(公告)号：US06410966B1
公开(公告)日：2002-06-25
申请号：US09880205
申请日：2001-06-13
IPC分类号： H01L2976
摘要： The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.
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