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14 条记录 (耗时 0.018 秒)

    Sampling frequency reproduction system
    2.
    发明授权
    Sampling frequency reproduction system 失效
    采样频率再现系统

    公开(公告)号：US5142420A

    公开(公告)日：1992-08-25

    申请号：US512998

    申请日：1990-04-23

    申请人： Hiroshi Tanaka ,  Tetsuo Ishiwata ,  Eiji Yamauchi

    发明人： Hiroshi Tanaka ,  Tetsuo Ishiwata ,  Eiji Yamauchi

    IPC分类号： G11B20/10 ,  H03L7/081 ,  H04N9/802

    CPC分类号： G11B20/10527 ,  H03L7/081 ,  H04N9/802

    摘要： A phase locked loop is disclosed in which a digital audio signal is recorded in synchronism with a video signal and a sampling frequency of the digital audio signal is reproduced in reproduction mode. A frequency divider of the phase locked loop comprising a phase comparator a low-pass filter, a VCO and a frequency divider unit is switched by the number of the digital audio signal recorded for each vertical sync period (or 1/N thereof) of the video signal, so that a sampling frequency of the digital audio signal having no relationship of integral ratio with a vertical sync frequency Fv of the video signal is reproduced from the same frequency Fv. The reference input to the phase comparator is delayed by a predetermined time in accordance with the number of the digital audio signal, with the result that the sampling frequency reproduced has no period error to the extent that the reference input has no period error.

    摘要翻译： 公开了一种锁相环，其中与视频信号同步地记录数字音频信号，并且在再现模式下再现数字音频信号的采样频率。 包括相位比较器的低通滤波器，VCO和分频器单元的锁相环的分频器通过为其垂直同步周期（或其1 / N）的每个垂直同步周期（或1 / N）记录的数字音频信号的数量进行切换 视频信号，使得与视频信号的垂直同步频率Fv无积分关系的数字音频信号的采样频率从相同的频率Fv再现。 根据数字音频信号的数量，相位比较器的参考输入被延迟预定的时间，结果是再现的采样频率没有周期误差，使得参考输入没有周期误差。

    Process for production of purified O-(2,6-dichloro-4-methyl-phenyl) O,O-dimethyl phosphorothioate
    5.
    发明授权
    Process for production of purified O-(2,6-dichloro-4-methyl-phenyl) O,O-dimethyl phosphorothioate 有权
    制备纯化的O-（2,6-二氯-4-甲基 - 苯基）O，O-二甲基硫代磷酸酯的方法

    公开(公告)号：US09024054B2

    公开(公告)日：2015-05-05

    申请号：US13133396

    申请日：2009-12-18

    申请人： Eiji Yamauchi ,  Ryuhei Wakita

    发明人： Eiji Yamauchi ,  Ryuhei Wakita

    IPC分类号： C07F9/18

    CPC分类号： C07F9/18

    摘要： A process for producing a purified O-(2,6-dichloro-4-methylphenyl)-O,O-dimethyl phosphorothioate, the process comprising: the first step of bringing a crude O-(2,6-dichloro-4-methylphenyl)-O,O-dimethyl phosphorothioate into contact with an acid; and the second step of recovering the purified O-(2,6-dichloro-4-methylphenyl)-O,O-dimethyl phosphorothioate from the mixture obtained in the first step.

    摘要翻译： 一种制备纯化的O-（2,6-二氯-4-甲基苯基）-O，O-二甲基硫代磷酸酯的方法，该方法包括：将粗O-（2,6-二氯-4-甲基苯基 ）-O，硫代磷酸二甲酯与酸接触; 和从第一步获得的混合物中回收纯化的O-（2,6-二氯-4-甲基苯基）-O，O-二甲基硫代磷酸酯的第二步骤。

    Apparatus for producing a video signal in synchronism with an external synchronizing signal
    7.
    发明授权
    Apparatus for producing a video signal in synchronism with an external synchronizing signal 失效
    用于与外部同步信号同步产生视频信号的装置

    公开(公告)号：US5929923A

    公开(公告)日：1999-07-27

    申请号：US740458

    申请日：1996-10-29

    申请人： Eiji Yamauchi ,  Kiyokazu Hashimoto ,  Tomoo Nakagawa

    发明人： Eiji Yamauchi ,  Kiyokazu Hashimoto ,  Tomoo Nakagawa

    IPC分类号： H04N9/65 ,  H04N5/04 ,  H04N9/877 ,  H04N9/896 ,  H04N11/04

    CPC分类号： H04N5/04 ,  H04N9/877 ,  H04N11/04 ,  H04N9/896

    摘要： An encoder generating an analogue color signal is configured by a digital circuit. An external frame signal supplied from an external apparatus is counted by a clock pulse signal generated by a crystal oscillator, and a synchronizing signal to be added to the luminance signal is produced on the basis of a counted results, and all horizontal synchronizing periods of digital active lines are made identical, and in vertical blanking period, a predetermined horizontal synchronizing period is made variable.

    摘要翻译： 产生模拟彩色信号的编码器由数字电路配置。 通过由晶体振荡器产生的时钟脉冲信号对来自外部设备的外部帧信号进行计数，并且根据计数结果产生要添加到亮度信号的同步信号，并且产生数字的所有水平同步周期 使活动线相同，并且在垂直消隐期间，使预定的水平同步周期变为可变。

    Video recording and reproducing apparatus
    8.
    发明授权
    Video recording and reproducing apparatus 失效
    视频记录和再现设备

    公开(公告)号：US5574568A

    公开(公告)日：1996-11-12

    申请号：US241002

    申请日：1994-05-11

    申请人： Tatsuro Juri ,  Eiji Yamauchi

    发明人： Tatsuro Juri ,  Eiji Yamauchi

    IPC分类号： H04N5/945 ,  H04N9/804

    CPC分类号： H04N9/8047 ,  H04N5/945

    摘要： In a recording apparatus for video signals, adjacent pixels in input image signals are collected as blocks and subjected to orthogonal transformation. Then, the dc component, control data, ac components, end-of-block signal and the like in a block after orthogonal transformation are coded and the codewords are arranged in prescribed record areas. One or a plurality of record areas forms a correction area, and error correction coding is performed and recorded on the data in a correction area. When record data are reproduced and recorded again, errors are detected in the unit of the error correction area. The dc component and the like in a record area wherein an error which cannot be corrected exists are replaced by a codeword which is not used ordinarily, and a codeword for the first ac component is replaced by an end-of-block codeword.

    摘要翻译： 在用于视频信号的记录装置中，将输入图像信号中的相邻像素作为块进行采集并进行正交变换。 然后，编码正交变换后的块中的直流分量，控制数据，交流分量，块结束信号等，并将码字配置在规定的记录区域。 一个或多个记录区域形成校正区域，并且执行纠错编码并将其记录在校正区域中的数据上。 当再现并再次记录记录数据时，以纠错区域为单位检测错误。 存在不能校正的错误的记录区域中的直流分量等被通常不使用的码字替代，并且第一交流分量的码字被块结束码字代替。

    Digital processing apparatus using two synchronization signals
    10.
    发明授权
    Digital processing apparatus using two synchronization signals 失效
    数字处理装置使用两个同步信号

    公开(公告)号：US5671260A

    公开(公告)日：1997-09-23

    申请号：US534512

    申请日：1995-09-27

    申请人： Eiji Yamauchi ,  Kiyokazu Hashimoto ,  Hidemi Oka ,  Takao Kashiro ,  Iwao Hidaka ,  Yoshiki Yamamoto

    发明人： Eiji Yamauchi ,  Kiyokazu Hashimoto ,  Hidemi Oka ,  Takao Kashiro ,  Iwao Hidaka ,  Yoshiki Yamamoto

    IPC分类号： H04N5/926 ,  H04N5/937 ,  H04N5/956 ,  H04L7/00 ,  H04L5/04 ,  H04L9/44

    CPC分类号： H04N5/956 ,  H04N5/926 ,  H04N5/937

    摘要： The digital processing apparatus includes a high speed response PLL that produces a first clock signal locked on the horizontal synchronization signal included in the video signal input thereto. An analog to digital converter converts the input video signal with respect to the first clock signal into a digitized video signal. A write controller controls a video memory to store the digitized video signal based on the first clock signal. A low speed response PLL produces a second clock signal based on the vertical synchronization signal included in the video signal. A read controller controls the video memory to read out the stored digitized video signal therefrom based on the second control signal. The digital processing apparatus can store and read the digitized video signal to and from the video memory stably, enabling the video signal read from the video memory to be processed effectively and securely.

    摘要翻译： 数字处理装置包括高速响应PLL，其产生锁定在输入到其中的视频信号中包括的水平同步信号的第一时钟信号。 模数转换器将输入视频信号相对于第一时钟信号转换为数字化视频信号。 写控制器控制视频存储器以基于第一时钟信号存储数字化视频信号。 低速响应PLL基于包括在视频信号中的垂直同步信号产生第二时钟信号。 读取控制器基于第二控制信号控制视频存储器从其读出存储的数字化视频信号。 数字处理装置可以稳定地将数字化视频信号存储到视频存储器中并从视频存储器读取视频信号，从而能够有效且可靠地处理从视频存储器读取的视频信号。