公开(公告)号：US06246624B1

公开(公告)日：2001-06-12

申请号：US09198726

申请日：1998-11-24

申请人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC分类号： G11C700

CPC分类号： H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

摘要： The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

摘要翻译： 本发明包括栅极和漏极与第一节点连接的第一MOS晶体管，栅极和漏极分别与第一节点和第三节点连接的第二MOS晶体管，第一电阻元件连接在第一节点之间 节点和第二节点，连接在第二节点和地电压端子之间的第二电阻元件，其输入端与第二节点连接的第一NOT电路，其输出端子是第四节点，并且连接在 第三节点和地电压端子，以及第二NOT电路，其输入端与第四节点连接，其输出端为第五节点。 因此，本发明能够以低功耗检测稳定状态的电压。

公开(公告)号：US06882193B2

公开(公告)日：2005-04-19

申请号：US10797253

申请日：2004-03-10

申请人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC分类号： G01R19/00 ,  G01R19/155 ,  G01R19/165 ,  G06F1/28 ,  G11C5/14 ,  G11C8/08 ,  G11C11/22 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

摘要： The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

摘要翻译： 本发明包括栅极和漏极与第一节点连接的第一MOS晶体管，栅极和漏极分别与第一节点和第三节点连接的第二MOS晶体管，第一电阻元件连接在第一节点之间 节点和第二节点，连接在第二节点和地电压端子之间的第二电阻元件，其输入端与第二节点连接的第一NOT电路，其输出端子是第四节点，并且连接在 第三节点和地电压端子，以及第二NOT电路，其输入端与第四节点连接，其输出端为第五节点。 因此，本发明能够以低功耗检测稳定状态的电压。

公开(公告)号：US06538482B2

公开(公告)日：2003-03-25

申请号：US09803775

申请日：2001-03-12

申请人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC分类号： H03L700

CPC分类号： H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

摘要： The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

公开(公告)号：US5864247A

公开(公告)日：1999-01-26

申请号：US817746

申请日：1997-07-09

申请人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC分类号： G01R19/00 ,  G01R19/155 ,  G01R19/165 ,  G06F1/28 ,  G11C5/14 ,  G11C8/08 ,  G11C11/22 ,  H03K17/22

CPC分类号： H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C11/22 ,  G11C5/143 ,  G11C8/08

摘要： The present invention includes a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

摘要翻译： PCT No.PCT / JP96 / 02295 371日期1997年7月9日第 102（e）1997年7月9日PCT PCT 1996年8月14日PCT公布。 公开号WO97 / 07408 日期：1997年02月27日本发明包括栅极和漏极与第一节点连接的第一MOS晶体管，栅极和漏极分别与第一节点和第三节点连接的第二MOS晶体管，第一电阻元件， 连接在第一节点和第二节点之间，连接在第二节点和地电压端子之间的第二电阻元件，输入端与第二节点连接的第一非电路，其输出端为第四节点， 并且其连接在第三节点和地电压端子之间，以及第二NOT电路，其输入端子与第四节点连接，并且其输出端子是第五节点。 因此，本发明能够以低功耗检测稳定状态的电压。

公开(公告)号：US06822493B2

公开(公告)日：2004-11-23

申请号：US10370395

申请日：2003-02-20

申请人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  Kouji Asari ,  Tatsumi Sumi

IPC分类号： H03L700

CPC分类号： H03K17/223 ,  G01R19/0084 ,  G01R19/155 ,  G01R19/16538 ,  G06F1/28 ,  G11C5/143 ,  G11C8/08 ,  G11C11/22

摘要： The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

公开(公告)号：US5953277A

公开(公告)日：1999-09-14

申请号：US037864

申请日：1998-03-10

申请人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

发明人： Toshio Mukunoki ,  Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Tatsumi Sumi ,  Nobuyuki Moriwaki

IPC分类号： G11C14/00 ,  G11C5/14 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22 ,  G11C11/22 ,  G11C11/401 ,  G11C7/02

CPC分类号： G11C11/22 ,  G11C5/147 ,  G11C7/06 ,  G11C7/14 ,  G11C7/22

摘要： A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.

摘要翻译： 参考电位发生器由两条信号线21和22组成; 用于向信号线21和22提供电荷的充电提供电路; 连接充电电路23和两条信号线21和22的第一连接电路24a和24b，以向两条信号线提供电荷; 以及通过第二控制信号将两条信号线21和22连接在一起的第二连接电路25，在由所提供的电荷确定的两个信号线的电位和信号线的每个负载电容的平均值之后，两条信号线断开。 结合上述参考电位发生器产生精确参考电位的本发明的半导体存储器件能够放大并输出参考电位与位线中的数据读出电位之间的电位差，由此“1” 或读出数据的“0”。

公开(公告)号：US5546342A

公开(公告)日：1996-08-13

申请号：US322543

申请日：1994-10-13

申请人： George Nakane ,  Toshio Mukunoki ,  Nobuyuki Moriwaki ,  Tatsumi Sumi ,  Hiroshige Hirano ,  Tetsuji Nakakuma

发明人： George Nakane ,  Toshio Mukunoki ,  Nobuyuki Moriwaki ,  Tatsumi Sumi ,  Hiroshige Hirano ,  Tetsuji Nakakuma

IPC分类号： G11C14/00 ,  G11C7/10 ,  G11C11/22 ,  G11C7/00

CPC分类号： G11C7/1006

摘要： The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value "1." This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.

摘要翻译： 通过使用多个存储单元并减小施加到存储数据值“1”的存储单元的电介质膜的应力，可以延长半导体存储器件的寿命。 这通过减少保留存储数据所需的重写次数在本发明中实现。 具体地，本发明利用反向和重写装置在读取之后将数据反转并重写到存储器单元中，用于存储指示当前存储的数据是否处于反转状态的信号的存储装置，以及用于判断数据 应该反向输出。

公开(公告)号：US5523974A

公开(公告)日：1996-06-04

申请号：US344680

申请日：1994-11-21

申请人： Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Nobuyuki Moriwaki ,  Toshio Mukunoki ,  Tatsumi Sumi

发明人： Hiroshige Hirano ,  George Nakane ,  Tetsuji Nakakuma ,  Nobuyuki Moriwaki ,  Toshio Mukunoki ,  Tatsumi Sumi

IPC分类号： G11C11/401 ,  G11C11/22 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/789

摘要： A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.

摘要翻译： 半导体存储器件包括主存储器单元，冗余存储器单元，冗余地址数据单元，其包括非易失性存储器，其电存储代替主存储单元中的故障存储器单元的冗余存储器单元的地址;控制器 电路15和冗余存储单元选择电路16.冗余存储单元选择电路用于保存从冗余地址数据单元读取的第一地址数据，并将第一地址数据与用于读或写的第二地址数据进行比较 通过控制电路输入的操作，从而选择主存储单元或冗余存储单元。

公开(公告)号：US5430671A

公开(公告)日：1995-07-04

申请号：US224589

申请日：1994-04-07

申请人： Hiroshige Hirano ,  Tatsumi Sumi ,  Yoshihisa Nagano

发明人： Hiroshige Hirano ,  Tatsumi Sumi ,  Yoshihisa Nagano

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor memory device comprising bit line, word line, plate electrode, ferroelectric capacitor having first electrode and second electrode, said second electrode being coupled to said plate electrode, MOS transistor the source of which is coupled to said first electrode, the gate is coupled to said word line and the drain is coupled to said bit line, and adjusting capacitor for adjusting bit line capacitance coupled to said bit line. The adjusting capacitor is provided to increase the potential difference for reading and control occurrence of operating errors.

摘要翻译： 一种半导体存储器件，包括位线，字线，平板电极，具有第一电极和第二电极的铁电电容器，所述第二电极耦合到所述平板电极，MOS晶体管的源极耦合到所述第一电极，栅极耦合 到所述字线，并且所述漏极耦合到所述位线，以及调整电容器，用于调整耦合到所述位线的位线电容。 提供调整电容器以增加用于读取和控制操作错误发生的电位差。

公开(公告)号：US5392234A

公开(公告)日：1995-02-21

申请号：US161328

申请日：1993-12-02

申请人： Hiroshige Hirano ,  Tatsumi Sumi ,  Nobuyuki Moriwaki ,  George Nakane

发明人： Hiroshige Hirano ,  Tatsumi Sumi ,  Nobuyuki Moriwaki ,  George Nakane

IPC分类号： G11C11/22 ,  G11C13/00

CPC分类号： G11C11/22

摘要： Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first Ferroelectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second Ferroelectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the Ferroelectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.

摘要翻译： 位线BL0和/ BL0连接到读出放大器SA0，第一MOS晶体管的栅极连接到第一字线WL0，第一铁电电容器Cs1的第一电极到第一Qn的源极，第一 Qn至BL0，Cs1的第二电极至第一平板电极CP0，第二MOS晶体管Qn的栅极至第二字线DWL0，第二铁电电容器Cd2的第一电极至第二Qn的源极，漏极 的第二Qn至/ BL0的第二电极，以及Cd1的第二电极到第二平板电极DCP0，并且在关闭第二Qn之后，DCP0的逻辑电压反转。 因此，在使用铁电元件的半导体存储器件中，虚拟存储电容器被可靠地初始化，并且能够在没有集中功耗的情况下实现高速读取。