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1.发明授权
公开(公告)号：US5331583A
公开(公告)日：1994-07-19
申请号：US76855
申请日：1993-06-15
申请人： Hirotaka Hara , Yukihito Ishihara , Masaru Kokubo
发明人： Hirotaka Hara , Yukihito Ishihara , Masaru Kokubo
CPC分类号： H03H17/06
摘要： A filter processing unit 2 receives the output of an oversampling-type analog/digital (A/D) converter circuit 1. Predetermined information is acquired by a compensation circuit 3-1 with predetermined timing from the filter processing unit 2 in the course of processing for producing a filter output for a predetermined integration-phase state and the predetermined information is fed back to the filter processing unit 2 as compensation information representing a difference in magnitude between a filter output with an integration phase lagging behind or leading ahead of the predetermined integration-phase state and a filter output with an unchanged integration phase in order to produce a controllable-phase filter output DMout. The timing for the acquisition of the compensation information by the compensation circuit 3-1 is controlled by a control circuit 7-1.
摘要翻译： 滤波处理单元2接收过采样型模拟/数字（A / D）转换器电路1的输出。在处理过程中，来自滤波处理单元2的预定定时由补偿电路3-1获取预定信息 用于产生用于预定积分相位状态的滤波器输出，并且将预定信息作为补偿信息反馈到滤波处理单元2，作为代表在累积相位滞后或超前于预定积分的积分相位的滤波器输出之间的幅度差的补偿信息 相位状态和具有不变积分相位的滤波器输出，以便产生可控相位滤波器输出DMout。 由补偿电路3-1获取补偿信息的定时由控制电路7-1控制。
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公开(公告)号：US4896318A
公开(公告)日：1990-01-23
申请号：US271673
申请日：1988-11-16
摘要： A method for cancelling an echo in a network termination (NT) of a transmission system and an apparatus therefor are disclosed. The method comprises the steps of detecting an end of transmission of a specific data train in an up-going signal when the phase of the received clock is to be shifted for synchronization during the transmission of the up-going signal from the NT, shifting the phase of the receiving clock when the end of transmission is detected, sampling a residual echo signal of the echo of the specific data train not cancelled by the adaptive filter, determining a correction value for the output of the adaptive filter and storing the correction value and adding a sign corresponding to the direction of the phase shift to the correction value after the phase shift and adding the result to the output of the adaptive filter to cancel the echo of the specific data train.
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公开(公告)号：US5097488A
公开(公告)日：1992-03-17
申请号：US614498
申请日：1990-11-16
CPC分类号： H04L7/0062 , H04J3/0608 , H04L7/042 , H04L7/08
摘要： A signal processing method and system in a receiving apparatus including a receiving equalizer circuit are provided for extracting transmission data from a received signal inputted via a transmission path every transmission frame having a predetermined synchronization pattern and transmission data. A phase error is detected from the received signal extracted in synchronism with a sampling signal in the receiving equalizer circuit. The frequency of the sampling signal is controlled until the phase error becomes minimum. In parallel, it is detected whether the frame synchronization pattern is present in the received signal in a predetermined interval or not. When the presence of the frame synchronization pattern is not detected after the phase has been stabilized by frequency control of the sampling signal, the sampling phase of the received signal is judged to be in the quasi-convergence state. Then the frequency of the sampling signal is forcibly changed largely. The frequency control of the sampling signal and detection of the frame synchronization pattern are repeated.
摘要翻译： 提供一种包括接收均衡器电路的接收装置中的信号处理方法和系统，用于经由传输路径输入的接收信号，每个传输帧具有预定的同步模式和传输数据。 从接收均衡器电路中的采样信号同步提取的接收信号中检测出相位误差。 控制采样信号的频率，直到相位误差变得最小。 并行地，检测帧同步模式是否以预定间隔存在于接收信号中。 当通过采样信号的频率控制使相位稳定之后没有检测到帧同步模式的存在时，接收信号的采样相位被判定为准收敛状态。 那么采样信号的频率就会被大大的改变。 重复采样信号的频率控制和帧同步模式的检测。
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公开(公告)号：US5018134A
公开(公告)日：1991-05-21
申请号：US444851
申请日：1989-12-04
摘要： A method for cancelling an echo in a network termination (NT) of a transmission system and an apparatus therefor are disclosed. The method comprises the steps of detecting an end of transmission of a specific data train in an up-going signal when the phase of the received clock is to be shifted for synchronization during the transmission of the up-going signal from the NT, shifting the phase of the receiving clock when the end of transmission is detected, sampling a residual echo signal of the echo of the specific data train not cancelled by the adaptive filter, determining a correction value for the output of the adaptive filter and storing the correction value and adding a sign corresponding to the direction of the phase shift to the correction value after the phase shift and adding the result to the output of the adaptive filter to cancel the echo of the specific data train.
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5.发明授权Semiconductor integrated circuit containing an automatic equalizer including a circuit for periodically updating a plurality of tap coefficients at varying frequencies 失效包含自动均衡器的半导体集成电路，包括用于周期性地更新变化频率的多个抽头系数的电路
公开(公告)号：US5327459A
公开(公告)日：1994-07-05
申请号：US697669
申请日：1991-05-09
申请人： Hirotaka Hara , Masaru Kokubo , Toshiro Suzuki
发明人： Hirotaka Hara , Masaru Kokubo , Toshiro Suzuki
CPC分类号： H04L25/03 , H03H21/0012
摘要： An automatic equalizer is capable of updating tap coefficients and constituted to vary the frequency at which to update the tap coefficients depending on the magnitude thereof. There are provided a plurality of ways to vary the frequency at which to update the tap coefficients. One way is to divide the taps into two groups, one group having its tap coefficients updated at a relatively high frequency, the other group having its tap coefficients updated at a relatively low frequency. Another way is to vary the frequency at which to update the tap frequency based on the result of suitably judging the magnitude thereof.
摘要翻译： 自动均衡器能够更新抽头系数，并且构成为根据其大小改变抽头系数的更新频率。 提供了多种方式来改变更新抽头系数的频率。 一种方式是将抽头分成两组，一组具有以较高频率更新的抽头系数，另一组具有以较低频率更新的抽头系数。 另一种方式是基于适当地判断抽头频率的大小来改变更新抽头频率的频率。
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公开(公告)号：US20120155301A1
公开(公告)日：2012-06-21
申请号：US13308635
申请日：2011-12-01
IPC分类号： H04W24/00
CPC分类号： H04W28/06 , H04L1/0002 , H04L1/0014 , H04L43/00 , H04L67/12 , H04L69/04 , H04L2001/0097 , H04W4/38 , H04W24/10 , H04W84/18 , Y02D70/00
摘要： A wireless communication device includes a sensor processing unit that generates sensor data including a measurement result acquired by a sensor; a communication measurement unit that generates communication quality data including a communication state for transmitting a packet; a compression determination unit that determines compression rates of first sensor data and first communication quality data according to the contents of the first sensor data including the transmitted sensor data and the generated sensor data or the contents of the first communication quality data including the transmitted sensor data and the generated communication quality data; a compression unit that compresses the first sensor data and the first communication quality data according to the determined compression rates; and a wireless communication unit that transmits a packet including the compressed first sensor data and the compressed first communication quality data to another wireless communication device or the access point.
摘要翻译： 无线通信装置包括传感器处理单元，其生成包括由传感器获取的测量结果的传感器数据; 通信测量单元，其生成包括用于发送分组的通信状态的通信质量数据; 压缩确定单元，其根据包括所发送的传感器数据和所生成的传感器数据的第一传感器数据的内容或包括所发送的传感器数据的第一通信质量数据的内容来确定第一传感器数据和第一通信质量数据的压缩率 和生成的通信质量数据; 压缩单元，其根据确定的压缩率压缩第一传感器数据和第一通信质量数据; 以及无线通信单元，其将包括压缩的第一传感器数据和压缩的第一通信质量数据的分组发送到另一无线通信设备或接入点。
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公开(公告)号：US08179733B2
公开(公告)日：2012-05-15
申请号：US13080958
申请日：2011-04-06
IPC分类号： G11C7/00
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
摘要翻译： 一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间 的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域 形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。 电源通道也与其他数字电路无关地形成。
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公开(公告)号：US07602665B2
公开(公告)日：2009-10-13
申请号：US12169253
申请日：2008-07-08
IPC分类号： G11C5/14
CPC分类号： H03L7/107 , G11C5/025 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/12 , G11C11/4076 , G11C29/02 , G11C29/023 , G11C29/028 , G11C29/12005 , H03L7/0814 , H03L7/0898 , H03L7/1072 , H03L2207/14
摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
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9.发明授权Filter control method, signal processing circuit and integrated circuit for wireless receiver 失效无线接收机的滤波器控制方法，信号处理电路和集成电路公开(公告)号：US07522896B2
公开(公告)日：2009-04-21
申请号：US11251922
申请日：2005-10-18
申请人： Takashi Oshima , Masaru Kokubo
发明人： Takashi Oshima , Masaru Kokubo
CPC分类号： H04B1/1027
摘要： A conventional method of controlling the passband of a filter involves an increase in cost for a chip due to a large area of a detection circuit for determining the level of an interference wave. The present invention utilizes a result obtained by detecting the amplitude level of a signal with an automatic gain control circuit to appropriately control the passband of a filter. The amplitude level of all the signals including a desired wave and an interference wave is detected by utilizing the automatic gain control circuit to thereby control the passband of a filter on the basis of the result.
摘要翻译： 控制滤波器的通带的常规方法涉及由于用于确定干扰波的电平的检测电路的大面积而导致芯片的成本增加。 本发明利用通过利用自动增益控制电路检测信号的幅度电平而获得的结果来适当地控制滤波器的通带。 通过利用自动增益控制电路检测包括期望波和干扰波的所有信号的振幅电平，从而基于结果控制滤波器的通带。
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公开(公告)号：US07339489B2
公开(公告)日：2008-03-04
申请号：US10786542
申请日：2004-02-26
申请人： Hiroshi Arita , Masaru Kokubo , Kenichi Mizugaki
发明人： Hiroshi Arita , Masaru Kokubo , Kenichi Mizugaki
IPC分类号： G08B23/00
CPC分类号： G08B25/10
摘要： A sensor transmits and receives wireless signals at intervals. A sensor unit, a processor 130, a wireless transmitter circuit, and a wireless receiver circuit are activated in sequence only for a fixed time when the electric power generated by a generator circuit and charged in a capacitor reaches a preset level. Sensing information detected by the sensor unit is processed by the processor circuit and, information on the number of receivable bytes is added to the processing results in the wireless receiver circuit. This added information is sent as sensor information to the wireless host from the wireless transmitting circuit, and the wireless receiver circuit that activated after the wireless transmitter circuit was activated, receives a control information signal from the wireless host. This received information is processed in the processor circuit.
摘要翻译： 传感器间隔地发送和接收无线信号。 传感器单元，处理器130，无线发射器电路和无线接收器电路仅在发电机产生的电力并在电容器中充电的电力达到预设电平的固定时间内被依次激活。 由传感器单元检测到的感测信息由处理器电路处理，并且关于可接收字节数的信息被添加到无线接收器电路中的处理结果。 该添加的信息作为传感器信息从无线发送电路发送到无线主机，并且在无线发射机电路被激活之后激活的无线接收机电路从无线主机接收控制信息信号。 该接收到的信息在处理器电路中被处理。
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