公开(公告)号：US5515047A

公开(公告)日：1996-05-07

申请号：US170411

申请日：1993-12-20

申请人： Kazuo Yamakido ,  Yoichiro Kobayashi ,  Masanori Otsuka ,  Takao Okazaki ,  Yukihito Ishihara ,  Norimitsu Nishikawa ,  Yuko Tamba

发明人： Kazuo Yamakido ,  Yoichiro Kobayashi ,  Masanori Otsuka ,  Takao Okazaki ,  Yukihito Ishihara ,  Norimitsu Nishikawa ,  Yuko Tamba

IPC分类号： H03M1/10 ,  H03M1/68 ,  H03M1/74 ,  H04B1/40 ,  H03M1/06

CPC分类号： H03M1/687 ,  H03M1/1019 ,  H03M1/745 ,  H03M1/747

摘要： The number of current sources and switches necessary for a plurality of unit D/A converters using equal reference currents, are drastically reduced to reduce the parasitic capacitance coupled to current output lines, by converting a plurality of digital signals of a predetermined bit, which are divided from an input digital signal, into an analog current unit D/A converters and by converting the analog current in a manner to correspond to the weights of the corresponding input digital signals, thereby to synthesize the currents. The fixed reference digital signal is inputted to the D/A converter for cancelling offsets. The offsets of a plurality of analog output signals in positive and opposite phases obtained by branching the output of the D/A converter are individually detected. After this, the DC offset values of the individual analog outputs are used as offset adjusted negative feedback signals for a desired value. One of them is the digital signal to be fed back to the input portion of the D/A converter whereas the other is the analog signal to be fed to a path portion obtained by branching the output of the D/A converter.

摘要翻译： 使用相同参考电流的多个单元D / A转换器所需的电流源和开关的数量被大大减少，通过转换预定位的多个数字信号来减小耦合到电流输出线的寄生电容， 从输入数字信号中分离成模拟电流单元D / A转换器，并通过转换模拟电流以对应于相应的输入数字信号的权重，从而合成电流。 固定参考数字信号被输入到D / A转换器以取消偏移。 分别检测通过分支D / A转换器的输出而获得的正相位和相位相位中的多个模拟输出信号的偏移。 之后，各个模拟输出的DC偏移值用作所需值的偏移调整负反馈信号。 其中一个是要反馈到D / A转换器的输入部分的数字信号，而另一个是要馈送到通过分支D / A转换器的输出而获得的路径部分的模拟信号。

公开(公告)号：US5331583A

公开(公告)日：1994-07-19

申请号：US76855

申请日：1993-06-15

申请人： Hirotaka Hara ,  Yukihito Ishihara ,  Masaru Kokubo

发明人： Hirotaka Hara ,  Yukihito Ishihara ,  Masaru Kokubo

IPC分类号： H03H17/08 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H03M3/04 ,  G06F15/31

CPC分类号： H03H17/06

摘要： A filter processing unit 2 receives the output of an oversampling-type analog/digital (A/D) converter circuit 1. Predetermined information is acquired by a compensation circuit 3-1 with predetermined timing from the filter processing unit 2 in the course of processing for producing a filter output for a predetermined integration-phase state and the predetermined information is fed back to the filter processing unit 2 as compensation information representing a difference in magnitude between a filter output with an integration phase lagging behind or leading ahead of the predetermined integration-phase state and a filter output with an unchanged integration phase in order to produce a controllable-phase filter output DMout. The timing for the acquisition of the compensation information by the compensation circuit 3-1 is controlled by a control circuit 7-1.

摘要翻译： 滤波处理单元2接收过采样型模拟/数字（A / D）转换器电路1的输出。在处理过程中，来自滤波处理单元2的预定定时由补偿电路3-1获取预定信息 用于产生用于预定积分相位状态的滤波器输出，并且将预定信息作为补偿信息反馈到滤波处理单元2，作为代表在累积相位滞后或超前于预定积分的积分相位的滤波器输出之间的幅度差的补偿信息 相位状态和具有不变积分相位的滤波器输出，以便产生可控相位滤波器输出DMout。 由补偿电路3-1获取补偿信息的定时由控制电路7-1控制。

公开(公告)号：US5259000A

公开(公告)日：1993-11-02

申请号：US236917

申请日：1988-09-23

申请人： Yasuyuki Kojima ,  Yasushi Yokosuka ,  Takeshi Shimanuki ,  Kazuhiko Takaoka ,  Yukihito Ishihara

发明人： Yasuyuki Kojima ,  Yasushi Yokosuka ,  Takeshi Shimanuki ,  Kazuhiko Takaoka ,  Yukihito Ishihara

IPC分类号： H04L27/00 ,  H04M11/06 ,  H04B1/38

CPC分类号： H04L27/0008 ,  H04M11/06

摘要： In a MODEM having modulation and demodulation circuits and a circuit for controlling the modulation and demodulation, a modulator-demodulator apparatus includes a register for accepting a macro-instruction from an external source; a circuit for interpreting and executing the macro-instruction; and a circuit for outputting a response to the macro-instruction, whereby the MODEM is controlled in response to the macro-instruction accepted from the outside source. The modulator-demodulator apparatus is suitably integrated over a single semiconductor substrate.

摘要翻译： 在具有调制和解调电路的调制解调器和用于控制调制和解调的电路的调制解调器中，调制器 - 解调器装置包括用于从外部源接受宏指令的寄存器; 用于解释和执行宏指令的电路; 以及用于输出对宏指令的响应的电路，由此响应于从外部源接受的宏指令来控制MODEM。 调制解调器装置适当地集成在单个半导体衬底上。

公开(公告)号：US5406218A

公开(公告)日：1995-04-11

申请号：US194074

申请日：1994-02-09

申请人： Yukihito Ishihara ,  Kazuo Yamakido ,  Takao Okazaki ,  Katsuhiro Furukawa

发明人： Yukihito Ishihara ,  Kazuo Yamakido ,  Takao Okazaki ,  Katsuhiro Furukawa

IPC分类号： H03D3/20 ,  H04L27/233

CPC分类号： H04L27/2332 ,  H03D3/20 ,  H03D2200/0039 ,  H03D2200/005

摘要： A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.

摘要翻译： 解调电路包括：相位检测电路，用于确定要解调的输入信号和参考信号之间的相位差的绝对值; 二进制相位检测电路，用于将输入信号和参考信号之间的相位超前或滞后转换为相位差的符号; 以及相位解调电路，用于从相位差的绝对值和符号计算输入信号和参考信号之间的相位差量，并对相位差量进行延迟检测; 其中二进制相位检测电路包括产生与相位检测电路的运算延迟相对应的延迟时间的延迟电路; 并且其中所述相位检测电路包括限制内部信号电压的电平限制器电路和参考电压调整电路以校正所述内部信号电压的偏差。

公开(公告)号：US6130577A

公开(公告)日：2000-10-10

申请号：US973899

申请日：1998-04-02

申请人： Yuko Tamba ,  Taiji Kondou ,  Katsuhiro Furukawa ,  Yukihito Ishihara

发明人： Yuko Tamba ,  Taiji Kondou ,  Katsuhiro Furukawa ,  Yukihito Ishihara

IPC分类号： H03L7/18 ,  H04L7/02 ,  H04L7/033 ,  H04L27/233 ,  H04L27/38 ,  H04L27/22

CPC分类号： H04L7/0066 ,  H04L27/2332 ,  H04L27/3881 ,  H04L27/389 ,  H04L7/0331 ,  H04L7/0337 ,  H03L7/18

摘要： In a digital demodulator for phase modulated signals, logical values of a waveform-shaped phase-modulated signal are sampled based on a clock signal having a period that stands in integer ratio relationship to a carrier period of the modulated signal and thereafter subjected to serial/parallel conversion for each predetermined interval, whereby a logical pattern of a digital code train subjected to the serial/parallel conversion is analyzed. As a result, phase information required to demodulate digital data can be logically detected.

摘要翻译： PCT No.PCT / JP96 / 01573 Sec。 371日期：1998年4月2日 102（e）1998年4月2日PCT PCT 1996年6月11日PCT公布。 出版物WO97 / 01908 日期1997年1月16日在相位调制信号的数字解调器中，基于具有与调制信号的载波周期成整数比的周期的时钟信号对波形相位调制信号的逻辑值进行采样， 然后对每个预定间隔进行串行/并行转换，由此分析经受串行/并行转换的数字代码串的逻辑模式。 结果，可以逻辑地检测解调数字数据所需的相位信息。

公开(公告)号：US5347279A

公开(公告)日：1994-09-13

申请号：US939594

申请日：1992-09-02

申请人： Yukihito Ishihara ,  Kazuo Yamakido ,  Yuko Tamba

发明人： Yukihito Ishihara ,  Kazuo Yamakido ,  Yuko Tamba

IPC分类号： H03M3/02 ,  H03M1/50

CPC分类号： H03M3/356 ,  H03M3/458

摘要： The difference between the output current of a voltage-current converter circuit and the output current of a local D/A converter circuit 2, whose output current is controlled by a feedback signal, is integrated by an analog circuit of which one end is connected to a DC potential point, and the voltage obtained by the integration thereof is quantized by a quantizing circuit. The result is integrated by a digital integrating circuit and is fed to a feedback correcting circuit 6 and, further, the result of A/D conversion is output. The feedback correcting circuit outputs a temporary feedback signal while the digital integration is being operated based on the output of the quantizing circuit. After the digital integrating operation completes the digital integration operation, a corrected feedback signal is generated instead of the temporary feedback signal. The signals inputted into the analog circuit 3 are continuously sampled even while the digital integration operation is being carried out.

摘要翻译： 电压电流转换器电路的输出电流与其输出电流由反馈信号控制的本地D / A转换器电路2的输出电流之间的差异由其一端连接到的模拟电路 DC电位点，并且通过其积分获得的电压由量化电路量化。 结果由数字积分电路集成，并被馈送到反馈校正电路6，并且进一步输出A / D转换的结果。 反馈校正电路在基于量化电路的输出操作数字积分的同时输出临时反馈信号。 在数字积分运算完成数字积分运算之后，产生经校正的反馈信号而不是临时反馈信号。 即使在进行数字积分操作时，输入到模拟电路3的信号也被连续取样。

公开(公告)号：US5200976A

公开(公告)日：1993-04-06

申请号：US614875

申请日：1990-11-16

申请人： Yukihito Ishihara ,  Yasuyuki Kozima ,  Atsushi Mizuno

发明人： Yukihito Ishihara ,  Yasuyuki Kozima ,  Atsushi Mizuno

IPC分类号： H04L27/18 ,  H04L7/033 ,  H04L7/04 ,  H04L7/10

CPC分类号： H04L7/0331

摘要： In a synchronizing circuit, such as a DPLL (Digital Phase-Locked Loop), adapted to be synchronized in accordance with clock signals of an external clock, a programmable timer in the circuit is forcedly reset in synchronism with the edge of an external clock signal pulse at the time of the clock signal's initial state in accordance with a clock detection circuit. Subsequently, baud timing of the external clock signals is detected by making use of internal clock signals produced by the circuit. Synchronism is thus established and maintained between the circuit and the external device.

摘要翻译： 在诸如DPLL（数字锁相环）的同步电路中，适于根据外部时钟的时钟信号同步，电路中的可编程定时器与外部时钟信号的边沿同步被强制复位 根据时钟检测电路在时钟信号的初始状态时的脉冲。 随后，通过利用由电路产生的内部时钟信号来检测外部时钟信号的波特率定时。 因此，在电路和外部设备之间建立并保持同步。